Lead Design Engineer

Job Title

Lead Design Engineer

Role Summary

Senior frontend digital/architecture engineer for advanced physical IP development. The role focuses on defining architecture, implementing RTL, and delivering high-performance PHY IP for industry serial interfaces.

Work within a cross-functional IP delivery team to produce production-quality IP, support bring-up and validation, and enable customer integration.

Experience Level

Senior. Requires 5+ years of industry experience with at least 3 years in ASIC design delivering IP and/or ASIC/SoC products.

Responsibilities

Primary responsibilities include driving architecture through RTL and coordinating with verification and system teams.

• Lead architecture, micro-architecture and RTL implementation for high-performance PHY IP (e.g., eUSB2v2, USB4-PHY, PCIe, ONFI, eDP/DP, SATA).
• Develop and refine feature requirements throughout the design lifecycle.
• Specify synthesis, constraint generation, power-management strategy and DFT requirements.
• Design and validate low-power features (power islands, state retention, isolation, etc.).
• Define coverage points, test strategy and stimulus with digital verification; support FPGA/Palladium testing.
• Coordinate delivery with project management and cross-functional teams: Analog, Layout, Backend, Firmware, Lab Bring-up/Validation, and Pre/Post-Silicon Engineering.
• Integrate IP into subsystems and support QA for customer releases and product validation.

Requirements

Key skills and experience required and preferred.

• Must-have: 5+ years industry experience; 3+ years in ASIC design delivering IP or ASIC/SoC products.
• Must-have: Deep knowledge of design architecture, RTL design/verification and ASIC end-to-end methodology.
• Must-have: Experience with synthesis, constraint generation, power management and DFT flows.
• Must-have: Practical knowledge of one or more industry serial standards (USB, DP, PCIe, Ethernet, etc.).
• Must-have: Understanding of analog mixed-signal basics, SI/PI, post-silicon validation and system-level behavior of physical interface IPs.
• Must-have: Strong cross-functional communication skills in English and Mandarin; ability to manage multiple priorities and work independently.
• Nice-to-have: Direct experience with high-speed serial link IPs in advanced technology nodes.
• Nice-to-have: Experience with SystemVerilog, Python, C/C++ and embedded microcontroller/DSP firmware.
• Nice-to-have: Experience using Cadence ASIC design tools.

Education Requirements

MS or BS in Electrical Engineering, Computer Engineering, Computer Science or a related technical field (MS/BS in Electrical/Computer Engineering explicitly listed in source).

About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.