Lead Design Engineer

Job Title

Lead Design Engineer

Role Summary

Lead the design and integration of complex SoC, subsystem, and IP blocks from architecture through RTL delivery and design closure. Own micro-architecture, RTL development, quality reviews, and cross-functional coordination with verification, physical design, DFT, firmware, and architecture teams.

Drive reusable, implementation-ready designs that meet power, performance, and area targets; mentor junior engineers and contribute to methodology and automation improvements.

Experience Level

Senior-level — preferred experience ~10–14 years in digital design (posting lists a broader range of 4–18 years).

Responsibilities

Primary responsibilities include end-to-end RTL implementation, subsystem integration, and cross-team technical leadership.

• Own RTL design and development for SoC, subsystem, and IP blocks; translate architecture and requirements into micro-architecture and implementation plans.
• Develop high-quality Verilog/SystemVerilog RTL with emphasis on correctness, reusability, and scalability.
• Design key blocks such as interconnects, controllers, bridges, memory interfaces, datapaths, and control logic.
• Drive block- and subsystem-level integration; resolve interface, timing, and functionality issues.
• Collaborate with verification, physical design, DFT, and firmware teams to ensure design quality and closure.
• Support lint, CDC, RDC, synthesis, STA constraints, DFT, and low-power checks; drive closure on design issues.
• Analyze and resolve design bugs found in simulation, emulation, silicon bring-up, or customer use cases.
• Mentor junior engineers and provide technical direction on coding practices, design quality, and methodology.

Requirements

Must-have technical skills and experience.

• 10–14 years of experience in digital design with strong exposure to IP, subsystem, and SoC development.
• Expertise in RTL design using Verilog/SystemVerilog.
• Strong understanding of digital design fundamentals: FSMs, pipelines, arbitration, buffering, and clock/reset design.
• Experience in micro-architecture definition and hardware implementation.
• Familiarity with AMBA protocols (AXI, AHB, APB) and designing interconnects, bus fabrics, DMA, and memory-mapped peripherals.
• Strong debugging skills for simulation, synthesis, and integration issues.
• Familiarity with lint, CDC, RDC, synthesis, STA constraints, DFT, and low-power design flows.
• Scripting experience in Python, Perl, Tcl, or Shell for automation.
• Strong communication and cross-functional collaboration skills.

Nice-to-have:

• Experience with PCIe, DDR, NoC, cache/coherency, security, or safety-related designs.
• Exposure to low-power methodologies (UPF/CPF), formal verification support, and silicon debug.
• Experience leading small design teams or owning major subsystems.

Education Requirements

Bachelor's or Master's degree (BE/BTech/ME/MTech) in Electronics, Electrical Engineering, Computer Engineering, or a related technical field.

About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.