Lead Debug/Trace/Profiling Design Engineer

Job Title

Lead Debug/Trace/Profiling Design Engineer

Role Summary

Technical lead responsible for architecting and delivering debug, trace and profiling IP for RISC-V-based SoCs. The role drives design from specification through integration, verification and documentation, working across architecture, performance, software and hardware teams.

Primary implementation uses hardware generators (Chisel/FIRRTL) and RTL; role includes customer and partner engagement and contribution to standards and tooling for debug/trace/profiling.

Experience Level

Senior — strong engineering lead with 7+ years of industry experience leading and directly contributing to architecture, microarchitecture and RTL design for debug/trace/profiling hardware.

Responsibilities

Key responsibilities include design, integration, verification and documentation of debug/trace/profiling hardware and related frameworks.

• Architect, design and implement debug, trace and profiling hardware for SoCs.
• Collaborate with architecture, performance, software and hardware teams on microarchitecture and specifications.
• Implement RTL generators with extensive configurability; ensure elements self-configure.
• Integrate designs into Chisel/FIRRTL framework and contribute framework improvements (automated docs, verification/testbench generation, packaged software).
• Perform initial sandbox verification and coordinate with design verification teams to create and execute verification plans.
• Create and maintain clear design documentation and transfer knowledge across teams.
• Engage with customers, partners, tools vendors and standards bodies to influence debug/trace/profiling solutions.

Requirements

Must-have technical skills, tools and behaviors.

• Deep knowledge of debug, trace and profiling architectures and concepts.
• Experience with debug interfaces (JTAG, cJTAG).
• Familiarity with CPU architectures, power management and SoC design.
• Experience with debugging tools and profiling methods.
• Proficiency in RTL design (Verilog, SystemVerilog, or VHDL).
• Experience in object-oriented or functional programming languages.
• Attention to detail, high-quality design focus and strong teamwork skills.
• Nice-to-have: Chisel/Scala experience, RISC-V architecture knowledge, familiarity with Git/Jira/Confluence.
• Successful offer contingent on background/reference checks, proof of right to work in France, and export-control authorization or ability to obtain necessary licenses.

Education Requirements

MS or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline.

About the Company

Company: SiFive

Headquarters: San Mateo, California, United States

SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.