Lead Application Engineer - Design Verification
Cadence Design SystemsJob Title
Lead Application Engineer - Design Verification
Role Summary
The Lead Application Engineer will support Cadence customers in evaluating, adopting, and deploying SoC verification, simulation, emulation/acceleration, and AI-enabled verification solutions. The role partners with Sales and corporate engineering to scope opportunities, run technical evaluations, and guide customer projects from proof-of-concept through training and handoff.
Experience Level
Senior — typically 4–6+ years of relevant industry experience in RTL design and verification.
Responsibilities
Primary responsibilities focus on customer-facing technical leadership, evaluations, and enablement.
- Work with Sales to identify and scope customer opportunities for verification, emulation/acceleration, and AI solutions.
- Plan and execute technical evaluations, benchmarks, and proof-of-concepts with existing and prospective customers.
- Train and ramp customers; provide ongoing technical support during customer projects.
- Deliver presentations, demos, and both basic and advanced training sessions as needed.
- Provide expert technical responses to complex customer queries and issues.
- Coordinate with corporate engineering and product teams to relay customer requirements and influence product direction.
Requirements
Required skills and experience are listed first; desirable items are noted as nice-to-have.
- Must-have: 4–6+ years of industry experience in RTL design and verification.
- Must-have: Design experience using Verilog or VHDL at IP or SoC level.
- Must-have: Verification experience with SystemVerilog/VHDL and HDL simulators.
- Must-have: Strong verbal and written Japanese; business-level English preferred.
- Must-have: Strong teamwork and communication skills for customer engagement.
- Nice-to-have: Experience with formal verification tools (Jasper is a plus).
- Nice-to-have: Experience with hardware emulators or accelerators.
- Nice-to-have: Familiarity with advanced verification methodologies such as UVM.
- Nice-to-have: Experience applying AI techniques to design and verification workflows.
Education Requirements
Not specified.
About the Company
Company: Cadence Design Systems
Headquarters: San Jose, California, USA
Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.
