Lead Analog Layout Design Engineer (SerDes/UCie)

Job Title

Lead Analog Layout Design Engineer (SerDes/UCie)

Role Summary

Lead technical layout engineer on the PMA custom layout design team within a SERDES product team. Responsible for delivering high-quality analog/mixed-signal layout for UCIe and high-speed SERDES IP from floorplanning through final verification.

Provide technical leadership, coordinate cross-functional integration at the PHY top level, and work with global teams across time zones.

Experience Level

Senior — minimum 7 years of experience in CMOS SERDES or high-speed I/O IC layout design.

Responsibilities

Primary duties include custom layout design, verification, and technical leadership for high-speed SERDES/UCIe IP.

• Design high-speed SERDES layouts for UCIe products at data rates up to 64 Gbps on advanced nodes (e.g., 2nm FinFET).
• Create quality analog/mixed-signal block layouts and collaborate closely with circuit designers.
• Manage back-end flow tasks from initial floorplanning through detailed layout and foundry DRC/LVS sign-off.
• Lead technical activities for block-level to PHY top-level integration and sign-off.
• Coordinate and collaborate with global teams across multiple time zones (including US west and east coast).
• Implement high-speed, high-accuracy cells, blocks and IP on schedule and to quality targets.
• Work with R&D/tool teams to enhance layout editing and verification tooling.
• Travel as required: approximately >10%.

Requirements

Must-have technical skills and experience for the role.

• Minimum 7 years of CMOS SERDES or high-speed I/O IC layout design and development.
• Proven experience with SERDES circuit blocks such as drivers, receivers, serializers/deserializers, phase interpolators, low-jitter PLLs, high-speed clock distribution, bias/bandgap, and voltage regulators.
• Experience delivering IP and test chips in collaboration with distributed custom layout and circuit design teams.
• Strong analog aptitude, solid problem-solving skills, and effective communication for cross-functional teamwork.
• Familiarity with back-end verification flows and foundry design-rule conformance.

Nice-to-have:

• Experience with Cadence tools and design experience at >10 Gbps and in process nodes <16 nm.
• Experience collaborating with Virtuoso, PVS or other layout tool developers to improve tooling.
• Interest in evolving analog/custom layout design methodologies.

Education Requirements

BEng, MEng, or PhD (as listed in the job qualifications).

About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.