Lead Analog Layout Design Engineer (SERDES/UCie)

Job Title

Lead Analog Layout Design Engineer (SERDES/UCie)

Role Summary

The Lead Analog Layout Design Engineer will provide technical leadership for PMA custom layout within the SERDES product team based in Cork, Ireland. The role focuses on analog/mixed-signal layout design, block-to-PHY integration and sign-off for UCIe high-speed SERDES IP targeting advanced process nodes.

The position requires collaboration with circuit designers, project managers and global layout teams across time zones to deliver production-quality IP and test chips.

Experience Level

Senior — minimum 7 years of experience in CMOS SERDES or high-speed I/O IC layout design and development.

Responsibilities

Key responsibilities include:

• Design high-speed SERDES for UCIe products at data rates up to 64 Gbps on advanced nodes (example: 2 nm FinFET).
• Create high-quality analog/mixed-signal layouts and take blocks through floorplanning, detailed layout and final foundry verification.
• Provide technical leadership for layout from block level to PHY top-level integration and sign-off.
• Collaborate with circuit designers, project managers and custom layout teams distributed globally.
• Contribute to layout tool/process improvements and interact with R&D teams when required.
• Deliver high-speed, high-accuracy cells, blocks and IP on schedule with high quality.

Requirements

Must-have:

• Minimum 7 years' experience in CMOS SERDES or high-speed I/O IC layout design and development.
• Proven layout experience with SERDES circuit blocks such as driver, receiver, serializer, deserializer, phase interpolator, low-jitter PLL, high-speed clock distribution, bias/bandgap and voltage regulators.
• Experience across the back-end flow: floorplanning, detailed layout and final design-rule/verification sign-off.
• Strong analog aptitude, problem-solving skills, effective communication and ability to work cooperatively in a team.
• Ability to work with global teams across different time zones.

Nice-to-have:

• Experience with Cadence tools and designs above 10 Gbps on nodes below 16 nm.
• Experience collaborating with layout/tool R&D (Virtuoso, PVS developers) to improve editing and verification tools.
• Interest in evolving analog/custom layout design paradigms.
• Willingness to travel (greater than 10%).

Education Requirements

BEng, MEng, or PhD (degree specified; no specific field of study or "equivalent experience" language provided).

About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.