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Lead Analog Design Engineer (Principal)

Marvell Technology
May 31, 2026
Full-time
On-site
Santa Clara, California, United States
$174,530 - $261,400 USD yearly
Semiconductor IP Jobs, Level - Senior

Job Title

Lead Analog Design Engineer (Principal)

Role Summary

Principal-level analog/mixed-signal engineer in Central Engineering responsible for architecture and hands-on design of high-speed SerDes and wireline transceiver analog IP for datacenter and AI connectivity.

Work includes research and development at the cutting edge of data rates, circuit implementation and verification, and cross-functional collaboration with system architects, digital designers and physical/layout teams. This position may require eligibility to access export‑controlled technology.

Experience Level

Senior — Principal level; typically 5–10 years of related experience.

Responsibilities

Primary responsibilities focused on analog circuit architecture, design, verification and support through silicon bring-up.

  • Architect and design analog/mixed-signal blocks (PLL, DLL, ADC, CTLE, regulators, amplifiers, TX, RX, CDRs) for high-speed SerDes/wireline transceivers.
  • Perform circuit simulation and verification using SPICE/Spectre, MATLAB and similar industry tools.
  • Collaborate with system architects, digital, layout/physical design and validation teams to meet performance and release targets for IP.
  • Supervise and review analog layout in deep submicron CMOS processes to achieve required signal integrity and performance.
  • Develop test plans, support silicon bring-up and debug issues through validation and production readiness.
  • Provide technical leadership and mentorship within the analog design team.

Requirements

Must-have technical skills and demonstrable experience.

  • Expertise in one or more areas: ADC/DAC, front-ends, CTLE, PLL, timing circuits, CDRs, SerDes.
  • Strong knowledge of deep submicron CMOS technologies and analog layout considerations.
  • Proven ability to collaborate across layout/physical design, system architecture, digital design and validation functions.
  • Excellent analytical, problem-solving and debug skills for full IP development cycle.
  • Hands-on experience with circuit verification and simulation tools (SPICE, Spectre, MATLAB).

Education Requirements

MS or PhD in Electrical Engineering. The posting indicates 5–10 years of related experience is typical for this role.


About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.

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Date Posted: 2026-05-29