Layout Engineer – DPG Layout

Job Title

Layout Engineer – DPG Layout

Role Summary

Implement block‑level and full‑chip physical layout for analog, mixed‑signal, and custom digital IP with a focus on manufacturability, quality, and turnaround time. Work on block ownership, verification closure, and integration activities while collaborating with Design, Verification, CAD, and senior layout engineers.

Experience Level

Mid-level - 3+ years of experience in analog/custom layout design in advanced CMOS processes.

Responsibilities

Primary responsibilities include:

• Implement physical layout for analog, mixed‑signal, and custom digital blocks and support full‑chip integration.
• Own block‑level layout execution with emphasis on quality, design intent, and on‑time delivery.
• Perform layout verification and closure activities: DRC, LVS, antenna checks, yield and quality checks.
• Use prompt‑based AI tools to generate or refine SKILL/Python/TCL scripts and automate repetitive layout and verification tasks.
• Support custom and semicustom integration to accelerate ECOs, alignment, and integration‑level updates.
• Collaborate with Design, Verification, CAD, and senior layout engineers to communicate status and risks.
• Review and mentor less‑experienced engineers on sub‑block layouts and practical techniques.

Requirements

Must‑have technical skills and experience:

• 3+ years of hands‑on analog/custom layout experience in advanced CMOS processes.
• Proven use of Cadence Virtuoso (VLE/VXL) and Calibre DRC/LVS, including ownership of verification and closure for assigned blocks.
• Layout experience with critical analog/mixed‑signal blocks (e.g. temperature sensors, PLLs, ADCs, DACs, LDOs, bandgaps, reference generators, charge pumps).
• Solid understanding of analog layout fundamentals: matching and symmetry techniques, electromigration, latch‑up, IR‑drop, coupling, crosstalk, and parasitics.
• Ability to interpret design constraints and produce robust, manufacturable layouts that meet performance targets (speed, capacitance, power, area).
• Hands‑on experience developing or applying AI‑driven automation and AI‑assisted methodologies for layout and verification tasks.
• Strong problem‑solving skills for physical layout verification and debug.

Nice‑to‑have:

• Exposure to memory layout environments (DRAM, SRAM, CAM, OTP).
• Experience with semicustom tools and ECO/integration acceleration techniques.

Education Requirements

Not specified.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.