Layout Design Staff Engineer
Lead layout development for DDR and HBM PHY IPs on advanced process nodes, delivering production-ready silicon IP. Work within a cross-functional engineering team to set technical direction, ensure layout quality, and reduce time-to-market.
Senior-level; requires 5+ years of relevant layout design experience (hands-on at advanced nodes such as 7nm and below).
The role focuses on technical leadership, hands-on layout work, and cross-functional collaboration to meet customer and product requirements.
Must-have technical skills and experience required for successful performance in this role. Education details are summarized separately below.
BTech or MTech in Electronics, Electrical Engineering, or a related field.
Company: Synopsys
Headquarters: Mountain View, California, USA
Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.
