Layout Design Staff Engineer

Job Title

Layout Design Staff Engineer

Role Summary

As a Staff Engineer on the memory IP physical-design team you will own full-custom layouts for embedded memories (SRAM, ROM, register files) across advanced nodes. The role covers floorplanning, power-grid and signal routing, physical verification, and cross-functional coordination with circuit and compiler teams.

Deliverables are manufacturable, signoff-ready memory macros used by customers in high-volume SoCs.

Experience Level

Senior - experience guidance from the posting: Diploma with 8+ years; BE/BTech with 6+ years; MS with 4+ years in layout or physical design.

Responsibilities

Primary responsibilities include:

• Design and own full-custom layouts for embedded memory blocks (SRAM, register files, ROM compilers) across advanced process nodes.
• Develop floorplans, place memory cells and periphery, and implement power grids and signal interconnects to meet area, performance, and power targets.
• Perform IR drop and electromigration analysis (e.g., XARA, RedHawk), back-annotate parasitics, and iterate with circuit teams to close timing and power.
• Execute physical verification using DRC/LVS tools (e.g., Calibre, ICV), debug violations, and drive layouts to signoff.
• Collaborate with memory compiler architects and circuit designers to translate specifications into manufacturable, verified layout deliverables.
• Script layout automation flows (TCL, Perl, C-shell) to improve productivity and consistency across memory variants.
• Support formal release cycles, documentation, design-rule checks, and handoff to product engineering and customers.

Requirements

Must-have technical skills:

• Deep hands-on experience with full-custom layout for embedded memories, including floor planning, placement, power-grid design, and routing.
• Proficiency with layout tools such as Cadence Virtuoso or Custom Compiler and physical-verification tools like Mentor Calibre or Synopsys ICV.
• Strong understanding of IR drop and electromigration analysis and experience with tools such as XARA or RedHawk.
• Solid knowledge of physical-design methodologies across floor planning, place-and-route, DRC/LVS verification, and signoff.
• Scripting ability in TCL, Perl, or C-shell to automate layout tasks.

Nice-to-have:

• Experience with memory compiler development, block placement, and parasitic-aware layout optimization.
• Prior customer engagement or mentoring experience.

Education Requirements

Diploma in Electronics Engineering with 8+ years of layout design experience; or BE/BTech with 6+ years; or MS with 4+ years in a directly relevant role (electronics/related engineering fields) as stated in the posting.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.