Layout Design Senior Engineer — Ho Chi Minh City
Design and deliver memory and standard-cell layouts for IP using advanced FinFET process nodes. Work on layout creation, verification, and automation within a global engineering team supporting silicon IP used across semiconductor products.
Senior — the posting specifies 2+ years of hands-on custom or memory/standard-cell layout experience.
Primary responsibilities include hands-on layout implementation, physical verification, and automation to produce tapeout-ready layouts that meet area, performance, and manufacturability targets.
Must-have technical skills and experience required to perform the role.
Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or a related field (as stated in the posting).
Company: Synopsys
Headquarters: Mountain View, California, USA
Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.
