Layout Design Manager

Job Title

Layout Design Manager

Role Summary

Lead a team responsible for physical layout of embedded SRAM memories and memory compilers across the full development cycle, from floorplanning through physical verification signoff and product release. The role focuses on delivering manufacturable memory IP that meets performance, power, area (PPA), reliability, and schedule targets through hands-on technical leadership and cross-functional collaboration.

Experience Level

Senior - typical requirement: 7+ years of hands-on SRAM memory layout development experience.

Responsibilities

The manager will combine hands-on layout expertise with people and project management to ensure memory IP delivery.

• Lead a team of SRAM layout engineers through floorplanning, layout implementation, physical verification, and product release.
• Own layout execution for bitcells, memory arrays, peripheral circuits, power distribution networks, and complete memory instances to meet PPA and manufacturability goals.
• Drive resolution of DRC/LVS/ERC, antenna issues, EM/IR analysis, routing congestion, and parasitic extraction problems at advanced nodes.
• Manage project schedules, resource allocation, dependencies, and risk across multiple concurrent memory and compiler efforts.
• Collaborate with circuit design, memory architecture, characterization, CAD/tool development, physical verification, process technology, and foundry teams.
• Develop and improve layout methodologies, automation, reuse frameworks, and standardization practices to reduce cycle time and improve quality.
• Mentor engineers, conduct performance reviews, support hiring and onboarding, and grow team technical capability.

Requirements

Must-have technical skills and experience.

• 7+ years of hands-on experience in SRAM memory layout development, including bitcells, arrays, peripheral circuits, and full memory integration.
• Deep understanding of SRAM architecture, memory compilers, and how layout affects performance, power, area, yield, and reliability.
• Strong working knowledge of DRC, LVS, ERC, antenna checks, EM/IR analysis, parasitic extraction, and advanced-node layout constraints.
• Demonstrated experience leading engineering teams or managing complex technical projects with multiple stakeholders.
• Proficiency with industry-standard custom layout tools and physical verification flows.
• Excellent cross-functional communication and ability to translate architecture/circuit requirements into concrete layout tasks.

Nice-to-have:

• Experience with layout automation, scripting, and methodology development.
• Experience with SRAM memory compiler development across multiple process technologies and advanced FinFET or GAA nodes.

Education Requirements

Bachelor's or master's degree in Electrical Engineering, Electronics, Microelectronics, or a related technical field.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.