Layout Design Manager

Job Title

Layout Design Manager

Role Summary

Lead a team responsible for layout of power-management integrated circuits (PMICs) targeting high power-density applications. Couple people leadership with technical ownership of layout execution, verification, and process/package trade-offs.

Drive new tools and flows, collaborate with circuit design, process, reliability, packaging, and foundry partners, and optimize thermal and electrical performance of advanced power solutions.

Experience Level

Senior - manager-level role with leadership responsibilities. Years of experience not specified.

Responsibilities

Core responsibilities include technical leadership of layout work, delivery, and cross-functional coordination.

• Lead and manage a layout engineering team developing PMICs for high-power-density applications.
• Own layout execution, verification, and sign-off for designs.
• Drive adoption and improvement of layout tools, verification flows, and design-for-manufacturability practices.
• Coordinate schedules, resource allocation, and design handoffs across design, product, process, reliability, packaging, and foundry teams.
• Mentor and develop junior layout engineers; establish standards and best practices.
• Define packaging and layout trade-offs to meet thermal, electrical, and reliability targets.
• Ensure on-time delivery and compliance with DRC/LVS/PEX and parasitic-extraction requirements.

Requirements

Must-have technical skills and leadership capabilities.

• Deep understanding of analog and power layout techniques (matching, symmetry, current density, electromigration, IR-drop management).
• Experience with high-voltage design rules, isolation techniques, and device spacing for BCD/HV processes.
• Experience with parasitic-aware layout for sensitive analog blocks (bandgaps, references, comparators, op-amps).
• Familiarity with power device layout, including LDMOS, power MOSFETs, bond pads, and ESD structures.
• Proficiency with Cadence Virtuoso and verification flows including DRC, LVS, PEX, and parasitic extraction.
• Knowledge of packaging considerations (bond wire, flip-chip, bump layout) as they relate to PMIC layout.
• Proven ability to manage schedules, resources, and cross-functional collaboration; strong verbal and written communication.
• Experience mentoring engineers, strong problem-solving, and time-management skills.

Nice-to-have:

• Experience with advanced power packages and thermal/electrical optimization for high-density power designs.
• Experience working directly with foundry and packaging partners.

Education Requirements

Bachelor's degree (degree level listed in source). Field of study not specified; the posting does not state whether equivalent practical experience is acceptable.

About the Company

Company: Texas Instruments

Headquarters: Dallas, Texas, USA

Texas Instruments is a global semiconductor company that designs, manufactures, and sells analog and embedded processing chips for various markets including industrial, automotive, and personal electronics. The company's innovations aim to make electronics more affordable and reliable, fostering advancements in technology through each generation of semiconductors.