Layout Design Manager

Job Title

Layout Design Manager

Role Summary

Lead a layout engineering organization delivering custom analog and mixed-signal IC layout for high-speed connectivity IP. Manage delivery from floorplanning through tapeout, establish layout methodologies and automation, and coordinate across design, verification, CAD, and product teams to ensure manufacturable production silicon.

Work directly influences data center, AI infrastructure, and networking products that use industry-leading SerDes and high-speed interfaces.

Experience Level

Senior - typically requires 10+ years in custom analog/mixed-signal IC layout and 3+ years managing layout engineering teams.

Responsibilities

Deliver and improve layout execution, standards, and team capability for advanced mixed-signal and high-speed IP.

• Lead and manage a layout engineering team delivering custom analog/mixed-signal IC layout for PCIe Gen7/Gen8, UCIe, SerDes, PLLs, PHYs, and power management IP.
• Direct layout execution from initial floorplanning through tapeout, including resource planning, schedule management, and risk mitigation across concurrent programs.
• Establish and implement advanced layout methodologies, automation frameworks, and AI-assisted design tools to improve quality and efficiency.
• Collaborate with analog design, digital implementation, verification, CAD, and product engineering to resolve technical challenges and align on project objectives.
• Define and enforce layout standards for DRC, LVS, EMIR, reliability, ESD, and manufacturing compliance across advanced CMOS process technologies.
• Recruit, mentor, and develop layout engineers and technical leads to build organizational capability.

Requirements

Key qualifications and experience required.

• 10+ years professional experience in custom analog/mixed-signal IC layout design with advanced CMOS process technologies.
• 3+ years of experience managing and developing layout engineering teams.
• Proven track record delivering high-speed SerDes, PLLs, PHYs, ADC/DACs, or power management circuits through multiple production tapeouts.
• Comprehensive knowledge of DRC, LVS, EMIR, reliability, ESD, and design-for-manufacturing requirements.
• Experience directing tapeouts, schedule management, and risk mitigation across concurrent development programs.
• Strong technical leadership, mentorship, and cross-functional communication skills.
• Nice-to-have: experience with PCIe, UCIe, or other high-speed interface standards; experience implementing automation frameworks or AI-assisted layout tools.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or equivalent professional experience. Equivalent practical experience is accepted.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.