Junior Physical Design Engineer (CPU)
Intel CorporationJob Title
Junior Physical Design Engineer (CPU)
Role Summary
Contribute to the physical implementation of CPU cores and subsystems from RTL to GDS under the guidance of senior engineers. Work on synthesis, place-and-route, timing/power analysis, and physical verification within a cross-functional CPU design team.
Experience Level
Entry-level (Level - Entry or Early Career). Typical background: recent graduate or engineer with approximately 0–3 years of combined educational and practical experience; role expects early-career contributors who will be mentored by senior staff.
Responsibilities
Primary responsibilities include supporting physical implementation tasks, performing analysis, debugging issues, developing scripts and flows, and collaborating with RTL, verification, and full-chip integration teams.
- Support physical design execution for CPU core or subsystem blocks (synthesis, place & route, timing closure).
- Perform static timing analysis, power analysis, and design rule verification to ensure PV convergence.
- Debug and resolve design issues with mentorship from senior engineers; participate in design reviews.
- Develop and maintain scripts and automation (TCL, Python or similar) to improve flows and productivity.
- Collaborate with RTL designers, verification engineers, and integration teams during block and full-chip flows.
- Document design work, test results, and contribute to best practices and team processes.
Requirements
Minimum technical skills and experience required for consideration; preferred items are listed separately.
- Must-have: Experience with integrated circuit design tools (Synopsys or Cadence toolsets) covering logic synthesis, place & route, static timing analysis, and design closure.
- Must-have: Experience or exposure to physical verification and convergence tasks (timing, power, DRC/LVS, noise, electromigration checks).
- Must-have: Scripting experience in TCL plus at least one other interpreted language (Python, Perl, Ruby, etc.).
- Must-have: Experience with synthesis of a digital logic block that was integrated into a larger SoC or IP flow.
- Nice-to-have: Familiarity with floor-planning, advanced routing techniques, clock distribution strategies, and RTL-to-GDS methodologies.
- Nice-to-have: Experience with Synopsys Fusion Compiler/ICC2/PrimeTime or Cadence Genus/Innovus toolchains, static timing/noise/reliability analysis, and formal equivalence flows.
- Behavioral: Strong learning agility, attention to detail, clear communication, adaptability, and ability to work collaboratively in a team.
Education Requirements
Bachelor's degree in Computer Engineering, Electrical Engineering, or a related technical field (with ~2+ years of combined educational or work experience), or a Master's in a related field (with ~3+ months of educational experience). Qualifications may also be met via a combination of relevant industry experience, internships, coursework, or research as described in the posting.
About the Company
Company: Intel Corporation
Headquarters: Santa Clara, California, USA
Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.
