ISP Design Engineer, up to Staff

Job Title

ISP Design Engineer, up to Staff

Role Summary

Design and deliver Image Signal Processing (ISP) hardware pipelines for SoC products. Work on micro-architecture, hardware datapaths, performance/accuracy modeling, PPA optimization, and pre-/post-silicon validation to achieve production-ready image quality for mobile, IoT, camera-centric, and embedded platforms.

Experience Level

Senior-level (role can be up to Staff). Expected to own complex ISP architecture and hardware execution; work cross-functionally with algorithms, verification, physical design, firmware, and system teams.

Responsibilities

Key responsibilities include:

• Architect, design, and optimize ISP modules: demosaic, noise reduction, color correction, tone mapping, sharpening, HDR merge, spatial/temporal filtering, etc.
• Translate imaging specifications and algorithms into hardware-friendly micro-architectures balancing image quality, area, power, and latency.
• Develop C/C++/SystemC models for validation, performance estimation, bandwidth analysis, and design-space exploration.
• Measure ISP performance using IQ metrics, throughput, latency, memory bandwidth, and power; propose quantitative improvements.
• Collaborate with verification to define test plans, reference model comparisons, coverage metrics, and debugging flows for pre-silicon validation.
• Work with physical design teams to meet PPA targets via pipeline design, timing strategies, and clock/power domain planning.
• Support post-silicon bring-up, tuning, debugging, and correlate silicon results with pre-silicon models.
• Produce architecture documentation, programming guides, and participate in cross-team design reviews.

Requirements

Must-have technical skills and experience (minimum qualifications—degree details are summarized under Education Requirements):

• Deep understanding of image signal processing algorithms and pipelines (demosaic, filtering, HDR, color pipelines, noise reduction).
• Strong RTL design skills in Verilog/SystemVerilog; experience in micro-architecture and datapath design.
• Proficiency in C/C++/SystemC and Python for modeling, simulation, and algorithm analysis.
• Experience with SoC integration, memory hierarchies, bandwidth and performance estimation, and low-power design techniques.
• Ability to collaborate cross-functionally and deliver designs from concept through silicon.
• Experience supporting verification, debugging, and performance correlation between models and silicon.
• Preferred: experience implementing ISP pipelines in hardware, computational photography or ML-based IQ, sensor pipeline knowledge, tuning workflows, FPGA experience, and scripting skills.

Education Requirements

Bachelor's, Master's, or PhD in Science, Engineering, or a related technical field are mentioned. Posting states examples: Bachelor's degree + 2+ years ASIC-related experience, Master's degree + 1+ year ASIC-related experience, or a PhD (field examples include Electrical Engineering, Computer Engineering, Computer Science, or related). The posting also allows equivalent practical experience in lieu of degree language.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.