IP RTL Senior Design Engineer

Job Title

IP RTL Senior Design Engineer

Role Summary

As an IP Logic Design Engineer on the Unified Intel Chassis IP team, you will design and deliver RTL for complex on-chip IP blocks focused on protocol bridges, security, telemetry, and reliability. The role partners with architects, validation, firmware, and post-silicon teams to ensure observability, RAS, and secure access-control for SoC integration.

This is an on-site position based in Bangalore, responsible for implementing debug hooks, telemetry capture, and error-handling flows that enable integration and post-silicon diagnostics.

Experience Level

Senior — minimum 8 years of experience in logic design and RTL development; 10+ years preferred for more advanced responsibilities.

Responsibilities

Primary responsibilities include RTL design, verification support, and delivering observability and reliability features for IP blocks.

• Develop RTL, microarchitecture, and simulations for IP blocks, functional units, and subsystems.
• Define and implement protocol bridges and privilege/policy propagation across AXI, AXI-Lite, APB, IOSF-SB, and HBW paths.
• Design parity/ECC generation and checking for request, response, and data channels.
• Implement secure MMIO, access-control/firewall logic, and privilege-based filtering.
• Define fault behavior (silent block semantics, RAZWI handling, poison propagation, timeouts) and RAS flows.
• Design telemetry, debug, and trace data paths, including counters, sticky status, snapshots, and firmware-visible CSRs.
• Integrate logging, interrupt, and firmware-visible error harvesting; support error injection and post-silicon debug hooks.
• Collaborate with architecture, validation, firmware, and post-silicon teams to ensure telemetry and debug signals are diagnosable and stable.
• Optimize RTL for power, performance, area, timing, and survivability trade-offs.

Requirements

Must-have technical skills and experience; preferred items noted.

• Minimum 8 years of experience in logic design and RTL development.
• Proficiency in Verilog and SystemVerilog.
• Strong understanding of digital design principles, including timing analysis, power optimization, and area trade-offs.
• Experience with industry-standard EDA tools for design and simulation (Synopsys, Cadence, Mentor Graphics).
• Knowledge of IP block integration workflows within SoC designs and experience supporting SoC customers during integration and verification.
• Expertise in RAS, debug, security, and telemetry functions; experience with transaction error handling.
• Strong knowledge of AXI-family protocols, parity/ECC schemes, and transaction error handling.
• Preferred: experience with UVM or formal verification techniques and demonstrated architecture/microarchitecture definition experience.

Education Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field is required. Master's or PhD in Electrical Engineering, Computer Engineering, or a related field is preferred.

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.