IP RTL Design Engineer
Marvell TechnologyJob Title
IP RTL Design Engineer
Role Summary
Member of Central Engineering responsible for architecting and delivering production-quality RTL for UCIe and other high-speed interface IP. The role spans micro-architecture definition through RTL delivery and involves close collaboration with architecture, verification, and downstream implementation teams.
The position balances hands-on implementation with technical leadership and mentoring of junior engineers.
Experience Level
Mid-level — 5–12 years of hands-on digital design experience delivering silicon-proven IPs or SoCs.
Responsibilities
The engineer will own micro-architecture and RTL implementation for medium-to-high complexity digital blocks and drive verification closure and production readiness.
- Architect, design, and implement RTL for UCIe and other high-speed interface IP.
- Own micro-architecture and RTL development for assigned blocks.
- Perform RTL coding, synthesis support, CDC/RDC analysis, linting, and debugging.
- Support test planning and silicon bring-up activities.
- Partner with Architecture and Verification teams to define test plans and coverage strategies.
- Participate in design reviews and contribute to IP quality, robustness, and reusability.
- Provide technical leadership: mentor junior engineers and review designs.
Requirements
Must-have technical skills and experience.
- Strong hands-on experience with SystemVerilog/Verilog (VHDL a plus).
- Domain expertise in high-speed protocols: UCIe preferred; Ethernet, DDR, PCIe, USB experience valued.
- Experience with RTL quality and sign-off flows, including lint and CDC/RDC tools (e.g., SpyGlass or equivalent).
- Understanding of synthesis, static timing analysis (STA), formal checking, and interactions with P&R teams.
- Familiarity with SoC architecture: processor cores, memories, interconnects, and peripheral interfaces.
- Proven ability to deliver production-quality designs on aggressive schedules; strong debugging and cross-functional collaboration skills.
Nice-to-have:
- Low-power design techniques and advanced clocking architectures.
- Exposure to post-silicon debug and silicon bring-up.
- Experience delivering reusable IP across multiple products or process nodes.
Education Requirements
BSEE or MSEE (or equivalent) in Electrical Engineering or a related technical field is specified. Equivalent practical experience may be considered.
About the Company
Company: Marvell Technology
Headquarters: Santa Clara, California, United States
Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.
