IP Manager, Design and Verification - Networking
NVIDIAJob Title
IP Manager, Design and Verification - Networking
Role Summary
Lead and manage a cluster of IP teams responsible for design and verification of complex hardware IP blocks for NVIDIA SmartNIC and DPU products. Own end-to-end IP delivery from micro-architecture and RTL through verification, synthesis handoff, and silicon readiness.
The role requires building high-performing teams, coordinating across architecture, SoC integration, physical design, software, and program management, and driving execution across multiple parallel IP projects.
Experience Level
Senior - typically requires 10+ years in ASIC/SoC design or verification, including 2+ years in people management or technical leadership.
Responsibilities
Accountable for delivery, quality, and scaling of design and verification efforts across a cluster of IPs.
- Lead, mentor, and grow design and verification engineers; define team structure, hiring plans, and career development.
- Own end-to-end IP execution: micro-architecture definition, RTL implementation, functional verification, coverage closure, assertions/formal work, and synthesis handoff.
- Define verification strategies, test plans, coverage goals, and sign-off criteria; oversee UVM-based constrained-random and directed test development and regression infrastructure.
- Coordinate with architecture, SoC integration, physical design, DFT, firmware, and software teams to resolve dependencies and ensure integration readiness.
- Identify risks early, drive trade-off decisions, and enforce milestone adherence and quality bars across IP projects.
- Improve design and verification methodologies, reuse strategies, and automation flows to increase productivity and IP quality.
- Manage multiple IPs/projects in parallel, balancing resources, schedules, and quality trade-offs.
Requirements
Must-have technical and leadership qualifications.
- 10+ years of experience in ASIC/SoC design or verification, with experience delivering IP across the full lifecycle.
- 2+ years of people management or technical leadership managing multi-engineer teams.
- Strong digital design fundamentals: RTL coding (Verilog/SystemVerilog), micro-architecture, timing, clocking, reset, power management, and synthesis constraints.
- Deep knowledge of verification methodologies: e-specman/UVM, constrained-random verification, coverage-driven verification, assertions (SVA), and formal techniques.
- Experience with EDA tools for simulation, lint, CDC, RDC, synthesis, and debug.
- Ability to communicate technical status, risks, and trade-offs clearly to engineering leadership and cross-functional partners.
- Preferred / Nice-to-have: experience with high-speed interfaces (PCIe, NVLink, HBM, DDR, high-speed SerDes); building verification infrastructure (regressions, CI/CD, emulation/FPGA prototyping); scripting/automation (Python, Perl, TCL, shell); background in GPU, networking, or AI/HPC IP domains.
Education Requirements
B.Sc. or M.Sc. in Electrical Engineering, Computer Engineering, or equivalent experience. Equivalent practical experience in relevant technical fields is acceptable.
About the Company
Company: NVIDIA
Headquarters: Santa Clara, California, USA
NVIDIA is a global leader in accelerated computing, renowned for its innovative solutions in AI and digital twins that transform diverse industries. The company specializes in networking technologies, providing end-to-end InfiniBand and Ethernet solutions for servers and storage that optimize performance and scalability. NVIDIA serves sectors such as high-performance computing, enterprise data centers, and cloud computing, constantly reinventing its products and services to stay ahead in the market.
