IP Logic Design Engineer

Job Title

IP Logic Design Engineer

Role Summary

Design and deliver RTL logic for high-performance IP blocks used in SoC products. Work with cross-functional teams (verification, digital backend, SoC integration) to define microarchitecture, meet PPA and timing goals, and support pre- and post-silicon validation.

Experience Level

Mid-level (Experienced hire). The posting expects experienced engineers; typical guidance is 6+ years of relevant logic design and RTL development experience.

Responsibilities

Key responsibilities for this role include:

• Deliver logic design and RTL implementation for IP development and ensure sign-off verification for functionality and synthesis.
• Create architecture and microarchitecture specifications and drive area, power, and performance optimizations.
• Perform RTL coding, simulation, and debug to meet timing and PPA targets.
• Collaborate with verification teams to review and execute verification plans and resolve failing RTL tests.
• Support SoC integration and ensure high-quality IP handoffs into full-chip designs.
• Drive post-silicon validation, debug, and manufacturing support for IPs.
• Coordinate with logic verification, digital backend, and SoC teams to align implementation and design objectives.

Requirements

Essential technical skills and experience; items listed as "Nice-to-have" are desirable but not mandatory.

• Must-have: 6+ years of hands-on experience in logic design and RTL development; expertise in SystemVerilog and RTL coding.
• Must-have: Experience with clock domain crossing (CDC), microarchitecture/simulation debugging, and static timing analysis.
• Must-have: Proficiency with low-power design techniques such as clock gating and UPF methodologies.
• Must-have: Familiarity with tool flows and checks: LINT, CDC/RDC, timing/synthesis tools, and regression/code-coverage methodologies.
• Must-have: Strong analytical skills and demonstrated ability to resolve pre-silicon and post-silicon design issues.
• Nice-to-have: Knowledge of AMBA protocols (CHI, AXI, AHB, APB), PCIe, and CXL.
• Nice-to-have: Experience in architecture/microarchitecture development for IP subsystems and working with physical design teams on timing/backend issues.
• Nice-to-have: Familiarity with mixed-signal designs, behavioral coding, and an understanding of PPA trade-offs.
• Nice-to-have: Strong communication skills and experience collaborating across geographically distributed teams.

Education Requirements

Minimum: Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field, typically coupled with 6+ years of relevant experience. Preferred: Master's degree in Electrical Engineering, Computer Engineering, or a related field (preferred candidates may list ~5+ years relevant experience).

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.