IO and Mixed Signal Layout Design Engineer

Job Title

IO and Mixed Signal Layout Design Engineer

Role Summary

Design and implement full-custom I/O and analog/mixed-signal layouts for planar and FinFET process technologies. Work within a chip/IP development team to deliver production-quality layout libraries and IP, drive floorplanning and placement decisions, and perform layout verification and debugging.

The role requires end-to-end ownership of layout deliverables, collaboration with circuit designers and cross-site teams, and mentoring junior engineers.

Experience Level

Senior - typically 8–12 years of relevant industry experience.

Responsibilities

Primary responsibilities for this role include:

• Design full-custom layouts of I/O libraries and analog/mixed-signal IP for planar and FinFET technologies.
• Drive floor-planning and placement decisions to meet performance, power, and routing constraints.
• Perform comprehensive layout verification and debugging (DRC/LVS/ANT/ERC/DFM and related checks).
• Generate LEF, support P&R requirements, and ensure full-chip integration requirements are met (IO frames, pitch, power planning, IO segments).
• Ensure ESD and latch-up protection implementation for I/O and analog layouts.
• Take ownership of deliverables from specification through sign-off and meet schedule/quality targets.
• Communicate with circuit designers and cross-site teams; lead and train junior engineers.

Requirements

Must-have technical skills and experience:

• Hands-on experience in I/O library and analog/mixed-signal IP development and verification.
• Solid understanding of planar and FinFET layout techniques and process constraints.
• Knowledge of full-chip concepts including IO frame/pitch, power planning, and IO segment rules.
• In-depth understanding of ESD and latch-up principles for I/O and analog layouts.
• Proficiency with Cadence Virtuoso Layout tools and Siemens Calibre verification tools.
• Expertise in layout verification and debugging: DRC, LVS, ANT, ERC, DFM checks, LPE, PERC, EM and IR analysis.
• Familiarity with physical design flow elements such as LEF generation and P&R handoff requirements.
• Demonstrated ability to lead projects, train junior engineers, and work independently within a team.

Nice-to-have:

• Experience with automation/AI tools for layout and scripting (SKILL or other scripting languages).

Education Requirements

B.Tech or M.Tech in Electronics/Electrical Engineering or a related technical discipline, or equivalent practical experience.

About the Company

Company: Broadcom

Headquarters: Irvine, California, United States

Broadcom is a global technology leader that designs, develops, and supplies a wide range of semiconductor and infrastructure software solutions. The company is known for its innovations in wireless and broadband communications, enabling a connected world.