IO and Mixed Signal Circuit Design Engineer

Job Title

IO and Mixed Signal Circuit Design Engineer

Role Summary

Work on the Mixed Signal and IO Library Development team in Central Engineering to design, verify and deliver IO interfaces and mixed-signal cells for advanced CMOS processes. The role covers circuit design, RTL/digital wrappers, physical design coordination, silicon validation support, and customer-facing specification work.

Experience Level

Mid-level — typically expected to have approximately 5–10 years of hands-on mixed-signal/analog circuit design experience.

Responsibilities

Key responsibilities include design, verification, integration and validation of IO and mixed-signal blocks.

• Design and verify IO interfaces and mixed-signal blocks (POR, process monitors, voltage/temperature sensors, crystal oscillators, etc.).
• Develop RTL, perform synthesis and verify digital wrappers that interface with analog circuitry.
• Collaborate with custom and P&R layout engineers; oversee physical design and verification flows.
• Create functional models and perform timing and characterization of cells for library integration.
• Engage with customers to gather requirements, define specifications, and implement circuits to meet those specs.
• Generate test infrastructure and vectors to support silicon validation on test chips; support ATE and bench validation.
• Produce technical documentation: datasheets, application notes, and integration guides.

Requirements

Must-have technical skills and tools for the role.

• Experience designing analog circuits such as PLLs, LDOs, bandgap references, ADCs or DACs; familiarity with AMS methodology and analog modeling is a plus.
• Proficient with Cadence Virtuoso schematic capture and ADE; experienced with Spectre and/or Hspice simulators.
• Working knowledge of LVS, DRC and EM/ESD verification tools (e.g. Totem, Pathfinder, PER).
• RTL coding, synthesis and verification experience for digital wrappers that interface to analog blocks.
• Ability to develop test vectors and infrastructure for silicon validation; experience supporting ATE or bench validation.
• Familiarity with physical design interactions and timing characterization of mixed-signal cells.
• Proficiency in automation/scripting (shell, SED, AWK, TCL, PERL or similar).
• Strong written and verbal English communication for cross-geography collaboration and customer interaction.

Education Requirements

Master of Science in Electrical Engineering (MSEE) required; posting specifies a minimum of approximately 5–10 years of hands-on experience designing mixed-signal circuits in advanced CMOS nodes (e.g., 5nm or 3nm).

About the Company

Company: Broadcom

Headquarters: Irvine, California, United States

Broadcom is a global technology leader that designs, develops, and supplies a wide range of semiconductor and infrastructure software solutions. The company is known for its innovations in wireless and broadband communications, enabling a connected world.