Intern - Verification Application Engineer
Cadence Design SystemsJob Title
Intern - Verification Application Engineer
Role Summary
The intern Verification Application Engineer will support customer engagements to solve functional verification challenges using simulation-based methodologies. The role covers pre-sales activities (presenting solutions) and post-sales technical support for functional verification products.
The role involves deploying and validating RTL and gate-level simulation flows, collaborating with R&D to influence tool and methodology roadmaps, and working directly with customers and internal teams.
Experience Level
Entry-level (Internship). Targeted at final-year students; no prior professional experience required beyond relevant coursework or project work.
Responsibilities
Primary responsibilities include customer-facing technical work across pre-sale and post-sale phases.
- Engage with customers to understand verification requirements and propose technical solutions.
- Demonstrate and present verification products and flows during technical campaigns.
- Deploy and validate advanced simulation flows for RTL and gate-level simulation (GLS).
- Provide post-sale technical support and troubleshooting for verification tools.
- Collaborate with R&D to report customer needs and influence product/methodology roadmaps.
- Document findings, reproduce issues, and present results to customers and internal teams.
- Work onsite from the Petah Tikva office 2–3 days per week as required by the internship.
Requirements
Key skills and attributes expected for successful candidates.
- Available 2–3 days per week onsite in Petah Tikva.
- Strong foundation in programming and scripting (examples: Python, C/C++).
- Basic understanding of digital design and verification concepts.
- Strong proficiency in at least one hardware description language or verification language (Verilog / SystemVerilog / VHDL / Specman-e).
- Good written and verbal communication skills in English; strong presentation and customer-facing skills.
- Motivation to learn verification methodologies, protocols, and tools; service-oriented and collaborative attitude.
- Nice-to-have: familiarity with UVM, experience with simulation-based flows (RTL and GLS), and prior hands-on verification project or lab experience.
Education Requirements
Bachelor's-level student in Electrical Engineering or Computer Engineering in the final year (1–2 semesters remaining). High academic performance required (GPA 85+ or equivalent).
About the Company
Company: Cadence Design Systems
Headquarters: San Jose, California, USA
Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.
