Intern - Verification Application Engineer
Support customer engagements by deploying and validating simulation-based verification flows (RTL and gate-level simulation) and providing technical product support. The role covers pre-sales demonstrations and post-sales troubleshooting while collaborating with customers, R&D, and verification teams.
Opportunity to develop verification skills working alongside experienced engineers.
Entry-level (intern). Final-year university student; part-time internship requiring 2β3 days per week on-site.
Primary tasks span pre-sales technical presentations and post-sales customer support.
Must-have technical skills, availability, and interpersonal abilities for the internship.
Final-year Bachelor's student in Electrical Engineering, Computer Engineering, or a related technical field (1β2 semesters remaining). Student position required. GPA 85+ (or equivalent high academic performance).
Company: Cadence Design Systems
Headquarters: San Jose, California, USA
Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.
