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Intern - Characterization and Support (Fall 2026)

Cadence Design Systems
August 31, 2026
Internship
On-site
San Jose, California, United States
$40 - $69 USD hourly
Test Engineering Jobs, Level - Entry or Early Career

Job Title

Intern - Characterization and Support (Fall 2026)

Role Summary

On-site internship within the Cadence DDR IP group in San Jose focused on post-silicon validation engineering. The intern will validate system-level and electrical performance of internal silicon test chips, debug issues with design teams, and produce characterization reports to support product functionality and reliability.

Experience Level

Internship / Entry-level. Intended for students with 0–2 years of relevant work experience; candidates should be enrolled in a Bachelor's or Master’s program.

Responsibilities

Primary responsibilities center on validating silicon, debugging issues, and delivering clear characterization results.

  • Validate system-level and electrical performance of internal silicon test chips.
  • Execute and maintain test plans, measurement procedures, and characterization workflows.
  • Debug silicon issues in close collaboration with analog and digital design teams.
  • Produce high-quality characterization and post-silicon validation reports.
  • Work cross-functionally to ensure product functionality, reliability, and deployment readiness.
  • Contribute to test automation and test infrastructure as required.

Requirements

Must-have technical skills, workplace skills, and legal/work-location requirements.

  • Strong fundamentals in analog and digital electronics, RTL, signal integrity, and control systems.
  • Strong analytical and problem-solving skills.
  • Excellent written and verbal communication; ability to work collaboratively in a team.
  • Able to work full-time hours in San Jose during the Fall semester (local candidates preferred).
  • Legal authorization to work in the United States.
  • Nice-to-have: prior experience in the semiconductor or electronics industry.
  • Nice-to-have: experience with script-based test automation (Python, C, or similar).

Education Requirements

Currently pursuing a Bachelor’s or Master’s degree in Electrical Engineering. The posting expects 0–2 years of relevant experience and ideally attendance at a local school so the candidate can work full-time in San Jose during the Fall; candidates must have legal authorization to work in the United States.


About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.

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Date Posted: 2026-08-29