Interconnect Design Engineer

Job Title

Interconnect Design Engineer

Role Summary

Senior/staff-level hardware engineer responsible for architecting and implementing TileLink interconnects, cache controllers, protocol bridges, and related infrastructure as configurable RTL generators. The role works within SiFive’s Chisel/FIRRTL framework and collaborates with verification, documentation, and software teams to deliver high-quality, performant interconnect IP.

Experience Level

Senior / Staff level. The posting indicates a senior staff engineer; explicit years of experience are not specified.

Responsibilities

Deliver RTL generator designs and integrate them into SiFive’s hardware-generator framework; collaborate on verification and documentation.

• Architect, design and implement TileLink interconnects, cache controllers, protocol bridges, and other uncore/infrastructure logic as RTL generators in Chisel.
• Implement self-configuring RTL generator elements that connect optimally across configurations.
• Design for multi-core and multi-system coherence to improve performance and efficiency.
• Provide extensive configurability as a first-class design consideration.
• Integrate new design content into the Chisel/FIRRTL framework and contribute improvements to enable automatic generation of documentation, verification testbenches, and packaged software.
• Perform initial sandbox verification and collaborate with the design verification team to create and execute full verification plans.
• Create and maintain clear design documentation and participate in collaborative design reviews.

Requirements

Must-have technical skills and experience for the role; followed by concise nice-to-have items.

• Knowledge of cache and cache-coherency architectures and concepts.
• Experience with NoC or other interconnect fabrics and ability to architect protocol-bridging solutions.
• Familiarity with industry bus protocols (AXI, AHB, APB, CHI).
• Strong software-engineering background: functional programming, object-oriented concepts, templated metaprogramming, and experience with compiler infrastructures or DSLs.
• Experience with data modeling and intermediate representations for optimization or transformation passes.
• Test-driven development mindset and ability to write adaptable unit tests.
• Proficiency in RTL design using Verilog, SystemVerilog, or VHDL.
• Attention to detail, high-quality design focus, and strong teamwork and collaboration skills.

Nice-to-have:

• Experience with Scala/Chisel, Bluespec, or other hardware-DSLs for configurable hardware generation.
• Knowledge of the RISC-V architecture.
• Experience using Git/GitHub, Jira, or Confluence.

Education Requirements

BS or MS in Electrical Engineering (EE), Computer Engineering (CE), Computer Science (CS) or a related technical discipline, or equivalent practical experience.

About the Company

Company: SiFive

Headquarters: San Mateo, California, United States

SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.