Interconnect Design Engineer

Job Title

Interconnect Design Engineer

Role Summary

Staff-level hardware engineer responsible for architecting, implementing, and integrating TileLink interconnects, cache controllers, protocol bridges, and other uncore infrastructure as configurable RTL generators. The role works within SiFive's CPU and interconnect IP teams and uses Chisel/Scala-based hardware construction and related verification flows.

Experience Level

Senior-level (staff). Specific years of experience not stated.

Responsibilities

Design, implement, verify, and document interconnect and uncore IP as configurable generators; integrate with SiFive's Chisel/FIRRTL framework and collaborate with verification and software teams.

• Architect, design and implement enhanced TileLink interconnects, cache controllers, protocol bridges, and other uncore logic as RTL generators in Chisel.
• Implement RTL generators that self-configure to connect optimally to other components.
• Improve multi-core and multi-system coherence for higher performance.
• Design extensive configurability as a first-class requirement.
• Integrate designs into the Chisel/FIRRTL framework and contribute framework improvements (documentation, verification testbenches, tests, and packaged software generation).
• Perform initial sandbox verification and collaborate with the design verification team to create and execute verification plans.
• Create and maintain clear documentation and participate in collaborative design reviews.

Requirements

Key technical skills and experience required; listed as must-have and nice-to-have.

• Must-have: Knowledge of cache and cache coherency architectures and concepts.
• Must-have: Experience with NoC or other interconnect fabrics and familiarity with bus protocols such as AXI, AHB, APB, or CHI.
• Must-have: Ability to architect solutions to connect bus fabrics of disparate protocols.
• Must-have: Strong software engineering background (functional programming, templated metaprogramming, compiler/DSL experience, data modeling, test-driven development).
• Must-have: Proficiency in RTL design using Verilog, SystemVerilog, or VHDL.
• Must-have: Attention to detail, focus on high-quality design, and ability to work collaboratively in teams.
• Nice-to-have: Experience with Scala/Chisel, Bluespec, or other DSLs for configurable hardware.
• Nice-to-have: Knowledge of the RISC-V architecture.
• Nice-to-have: Experience with Git/GitHub, Jira, Confluence.

Education Requirements

BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline, or equivalent practical experience.

About the Company

Company: SiFive

Headquarters: San Mateo, California, United States

SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.