Interconnect Design Engineer

Job Title

Interconnect Design Engineer

Role Summary

Join SiFive's interconnect and uncore team to design and implement TileLink-based interconnects, cache controllers, protocol bridges, and related infrastructure as configurable RTL generators. The team develops hardware using Chisel/Scala and integrates design, verification, and documentation workflows.

This is a junior hardware engineer role focused on developing high-quality, configurable interconnect IP for multicore SoCs.

Experience Level

Entry-level / Junior — role described as a "junior hardware engineer". Suitable for candidates with early-career experience (approximately 0–3 years) or equivalent practical experience.

Responsibilities

Design, implement, verify, and document interconnect and uncore IP as configurable generators.

• Architect and implement TileLink interconnects, cache controllers, protocol bridges, and other infrastructure logic in Chisel as RTL generators.
• Implement self-configuring generator elements to allow optimal interconnection across configurations.
• Improve multi-core and multi-system coherence performance and efficiency.
• Design extensive configurability and integrate new content into the Chisel/FIRRTL framework.
• Perform initial sandbox verification and collaborate with the design verification team on comprehensive test plans.
• Create and maintain documentation and support knowledge sharing across the team.

Requirements

Must-have technical skills and experience are listed below. Education-related items are summarized separately under Education Requirements.

• Knowledge of cache and cache coherency architectures and concepts.
• Experience with NoC or other interconnect fabrics and industry-standard bus protocols (AXI, AHB, APB, CHI).
• Ability to architect solutions that connect bus fabrics with disparate protocols.
• Strong software engineering background, including functional programming and test-driven development.
• Familiarity with templated metaprogramming, compiler infrastructures for DSLs, and data modeling / IR transformations.
• Proficiency in RTL design using Verilog, SystemVerilog, or VHDL.
• Attention to detail, focus on high-quality design, and ability to work collaboratively in a team.

Nice-to-have:

• Experience with Scala/Chisel, Bluespec, or other DSLs for configurable hardware generation.
• Familiarity with RISC-V architecture.
• Experience with Git/GitHub, Jira, and Confluence.

Education Requirements

BS or MS in Electrical Engineering (EE), Computer Engineering (CE), Computer Science (CS) or a related technical discipline, or equivalent practical experience.

About the Company

Company: SiFive

Headquarters: San Mateo, California, United States

SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.