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Integrated Circuit Designer

MIT Lincoln Laboratory
June 12, 2026
Full-time
On-site
Lexington, Massachusetts, United States
$145,200 - $220,000 USD yearly
ASIC Design Jobs, Level - Mid-Career

Job Title

Integrated Circuit Designer

Role Summary

Join the Advanced Imager Technology Group to design next-generation readout integrated circuits for imaging systems. The role spans concept, modeling, physical implementation, and tapeout within a vertically integrated team that develops imagers, detectors, and readout electronics.

Experience Level

Mid-level. Candidates are expected to have several years of hands-on IC design experience; advanced qualifications and multi-year experience in nanoscale design are preferred.

Responsibilities

Work as a member of an IC design team to develop readout architectures and implement designs for prototype and system demonstrations.

  • Develop readout and processing integrated circuit architectures from concept through tapeout.
  • Perform circuit modeling, RTL/HDL development, simulation, synthesis, and verification as applicable.
  • Execute physical implementation tasks including place-and-route, timing closure, and layout for advanced nodes.
  • Collaborate with device, packaging, and system teams to integrate ICs into imaging systems.
  • Address signal integrity, parasitics, power management, and manufacturability at nanoscale nodes.
  • Document design decisions and participate in design reviews and cross-disciplinary integration activities.

Requirements

Must-have skills and conditions; candidates should demonstrate deep expertise in multiple technical areas below.

  • Deep expertise in at least two of: digital IC design, industry-standard IC design flows (Cadence/Mentor/Synopsys), HDL programming and simulation, synthesis and place-and-route, functional verification, timing analysis, scripting (Python/Perl).
  • Experience with advanced-process design kits, FinFET/multi-gate transistor techniques, multi-patterning, litho-friendly practices, and low-power techniques for sub-22nm nodes.
  • Familiarity with parasitic extraction, signal integrity, DFM practices, power management and leakage mitigation in advanced nodes.
  • Preferred: full-custom design and physical verification experience; familiarity with imaging systems or digital signal processing.
  • Ability to work in a collaborative, interdisciplinary team and contribute to continuous improvement and knowledge sharing.
  • U.S. citizenship is required; selected candidate must be able to obtain and maintain a Secret-level DoD security clearance and pass a background investigation.

Education Requirements

Ph.D. in Electrical Engineering, Computer Engineering, or a related field preferred. Candidates with an M.S. plus 5+ years of relevant experience will be considered. Related technical fields and equivalent practical experience are acceptable.


About the Company

Company: MIT Lincoln Laboratory

Headquarters: Lexington, Massachusetts, United States

A federally funded research and development center operated by MIT that develops advanced technologies for national security and scientific applications, including sensors, imaging systems, integrated circuits, electronics, and systems engineering.

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Date Posted: 2026-06-12