Infra Systems Physical Architect

Job Title

Infra Systems Physical Architect

Role Summary

Work on physical architecture and implementation of high-performance NoC (Network-on-Chip) within the Infra Systems Architecture team. Focus on floorplan-driven NoC design, physically aware methodologies, and optimization for power, performance, and area (PPA).

Collaborate with cross-functional SoC teams to define, model, optimize, verify, and document IP and SoC-level implementations and produce custom implementation techniques.

Experience Level

Senior-level. Preferred industry experience: 5+ years in NoC/ASIC design; minimum experience expectations vary by degree (see Education Requirements).

Responsibilities

Deliver physically aware NoC architectures and implementation methodologies to meet latency, area, performance, and power targets.

• Define and model NoC physical architectures and floorplans; drive floorplan-informed implementation decisions.
• Develop physically aware synthesis recipes and specialized placement strategies for synthesis and place & route.
• Design clocking strategies including spine and mesh CTS and source-synchronous clock routing.
• Perform timing, power, area, and signal-integrity analysis; drive timing closure for complex MMMC designs.
• Specify and improve physical-aware DFT and testability constraints used during synthesis and P&R.
• Optimize routing to reduce wire delays and meet performance targets.
• Estimate and plan NoC implementations for future product needs.
• Automate flows and tool usage through scripting and maintain tool integrations.

Requirements

Core technical skills and proven implementation experience required. Tool experience and formal methods are advantages.

• Must-have:
  • NoC implementation experience (AMBA and cache-coherency mechanisms)
  • Constraining and timing analysis with timing-closure experience
  • Physical-aware synthesis and physical design experience
  • Physical-aware DFT and testability constraints
  • Clock tree planning (spine, mesh CTS) and source-synchronous clock routing
  • Custom placement and routing strategies
  • Power domain analysis and experience addressing SI/timing tradeoffs
  • Scripting and software skills: Python, Perl/TCL, Linux/Unix shell, and C
• Nice-to-have:
  • Experience with Design Compiler, Fusion Compiler, Genus, PrimeTime, PrimePower, Innovus
  • Formal verification experience
  • Prior work on high-performance SoCs and MMMC designs

Education Requirements

Bachelor's degree in Science, Engineering, or related field plus 6+ years of ASIC design/verification/validation/integration experience; OR Master's degree in Science, Engineering, or related field plus 5+ years; OR PhD in Science, Engineering, or related field plus 4+ years.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.