Infra Power Design Verification Sr Staff Engineer

Job Title

Infra Power Design Verification Sr Staff Engineer

Role Summary

Senior verification engineer responsible for developing UVM-based verification environments and driving verification closure for high-speed interconnect and infrastructure IP in ASIC/SoC subsystems. The role partners with RTL designers, architects, and validation teams to ensure correctness, coverage, and performance targets.

Experience Level

Senior. Typical hires have substantial ASIC/SoC verification experience (commonly 8+ years); minimum experience requirements vary by education (see Education Requirements).

Responsibilities

Key responsibilities focus on protocol verification, coverage, and mentoring.

• Develop and maintain UVM-based verification environments for high-speed interconnects (PCIe, CXL, AXI).
• Create and execute verification plans at block and top levels, including functional coverage, assertions, and regressions.
• Implement and enhance scoreboards, agents, monitors, sequences and integrate third-party VIPs for protocol compliance.
• Integrate and validate SMMU and Coresight components within subsystem environments.
• Debug RTL and gate-level simulation failures and drive coverage convergence to achieve verification closure.
• Collaborate with design, architecture, and validation teams to derive verification strategies from specifications.
• Contribute to performance, power, and cost optimization considerations during verification and validation.
• Mentor junior engineers and improve verification methodology and processes.

Requirements

Must-have technical skills and practical experience required for successful performance in this role.

• Strong proficiency in SystemVerilog, UVM, and modern verification methodologies.
• Deep, hands-on experience with PCIe (Gen3–Gen6), CXL (1.1–3.0), AXI/CHI protocols, and SMMU/Coresight architecture.
• Experience using Synopsys or Mentor VIPs for PCIe/CXL and AMBA protocols.
• Expertise in assertion-based verification (SVA), coverage-driven testing, and random constraint-based verification.
• Proficiency with scripting for automation (Python, Perl, Tcl).
• Knowledge of power-aware verification (UPF), formal verification techniques, and power/performance optimization.
• Proven ability to debug complex RTL and gate-level simulation issues and close coverage gaps.
• Experience mentoring engineers and improving verification methodologies.
• Nice-to-have: exposure to post-silicon validation, lab bring-up, and additional peripheral protocols (USB, Ethernet).

Education Requirements

Degree and experience options specified: Bachelor’s, Master’s, or PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or a related technical field. Equivalent practical experience is accepted. Minimum experience varies by degree: Bachelor’s +6 years, Master’s +5 years, PhD +4 years. Preferred candidates may have 8–12+ years of ASIC/subsystem/SoC verification experience.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.