Infra Design Verification Sr Lead Engineer

Job Title

Infra Design Verification Sr Lead Engineer

Role Summary

Lead verification engineer responsible for developing and maintaining UVM-based verification environments and verification plans for high-speed interconnects and subsystem components. Collaborates with RTL designers, architects, and validation teams to ensure functional correctness, coverage closure, and performance/power trade-offs. Mentors junior engineers and drives verification methodology improvements.

Experience Level

Senior. Experience guidance: minimum 1–2 years in hardware engineering or related work per the posting; preferred 3+ years of ASIC/Subsystem/SoC verification experience.

Responsibilities

Key responsibilities include design and execution of verification environments, closure activities, and cross-team collaboration.

• Develop and maintain UVM-based verification environments for high-speed interconnect protocols (PCIe, CXL, AXI).
• Create and execute verification plans for PCIe, CXL, AXI, and CHI protocols.
• Perform block-level and top-level verification: functional coverage, assertions, and regression testing.
• Collaborate with RTL designers, architects, and validation teams to ensure design correctness and coverage convergence.
• Use third-party VIPs (Synopsys/Mentor) for protocol compliance and simulation.
• Implement and enhance scoreboards, agents, monitors, and sequences.
• Integrate and validate SMMU and Coresight components within subsystem environments.
• Drive verification closure through coverage convergence and assertion-based techniques.
• Contribute to performance, power, and cost optimization considerations during verification.
• Mentor junior engineers and improve verification methodology and processes.
• Debug failures at RTL and gate-level simulations.

Requirements

Must-have technical skills and tools.

• Strong proficiency in SystemVerilog, UVM, and verification methodologies.
• Deep understanding of PCIe Gen3/Gen4/Gen5/Gen6, CXL 1.1/2.0/3.0, AXI/CHI protocols, and SMMU/Coresight architecture.
• Familiarity with Synopsys/Mentor VIPs for PCIe/CXL and AMBA protocols.
• Expertise in assertion-based verification (SVA) and coverage-driven testing.
• Proficiency in scripting for automation (Python, Perl, Tcl).
• Knowledge of power-aware verification (UPF), formal verification, and performance/power optimization techniques.
• Experience with random constraint-based testing, coverage collection, and regression management.
• Experience debugging RTL and gate-level simulation failures.

Nice-to-have:

• Experience with peripheral protocols such as USB or Ethernet.
• Post-silicon validation and lab bring-up exposure.

Education Requirements

Bachelor's in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field (commonly listed with 2+ years hardware engineering experience) OR Master's in those fields (commonly listed with 1+ year experience) OR PhD in those fields. Preferred degrees include Bachelor's/Master's/Ph.D. in Electrical, Electronics, or Computer Engineering.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.