Infra Design Verification Sr Lead Engineer

Job Title

Infra Design Verification Sr Lead Engineer

Role Summary

Lead verification engineer responsible for planning and executing UVM-based verification for high-speed interconnects and subsystem interfaces in SoC/Subsystem designs. Works closely with RTL designers, architects, validation, and bring-up teams to ensure protocol compliance, coverage closure, and performance/power trade-offs.

Experience Level

Senior — typically 6–10+ years of ASIC/Subsystem/SoC verification experience. Minimum experience guidelines vary by degree (see Education Requirements).

Responsibilities

Key responsibilities include design and delivery of verification environments and driving verification closure for infra/interconnect blocks and subsystem integrations.

• Develop and maintain UVM-based verification environments for high-speed interconnects (PCIe, CXL, AXI).
• Create and execute verification plans; define functional coverage and assertion strategies.
• Perform block-level and top-level verification, including regression testing and coverage analysis.
• Collaborate with RTL designers, architects, and validation teams to resolve functional issues and close coverage gaps.
• Use third-party VIPs (Synopsys, Mentor) for protocol compliance and simulation.
• Implement and enhance scoreboards, agents, monitors, and stimulus sequences.
• Integrate and validate SMMU and Coresight components in subsystem environments.
• Drive verification closure through coverage convergence and assertion-based verification.
• Contribute verification input for performance, power, and cost optimization.
• Mentor junior engineers and improve verification methodology; debug RTL and gate-level failures.

Requirements

Technical must-have skills and tools; preferred items noted separately.

• Must-have: Strong proficiency in SystemVerilog, UVM, and verification methodologies.
• Must-have: Deep protocol knowledge: PCIe Gen3/Gen4/Gen5/Gen6, CXL 1.1/2.0/3.0, AXI/CHI, and SMMU/Coresight architecture.
• Must-have: Experience with assertion-based verification (SVA), coverage-driven testing, and random constraint-based verification.
• Must-have: Familiarity with Synopsys/Mentor VIPs for PCIe/CXL and AMBA protocols.
• Must-have: Proficiency in scripting for automation (Python, Perl, Tcl).
• Must-have: Experience driving coverage closure, regression infrastructure, and debug at RTL/gate level.
• Nice-to-have: Knowledge of UPF/power-aware verification, formal verification, and performance/power optimization techniques.
• Nice-to-have: Experience with post-silicon validation, lab bring-up, and peripheral protocols (USB, Ethernet).
• Nice-to-have: Demonstrated mentoring or technical leadership on verification teams.

Education Requirements

Degree required with experience alternatives: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with 3+ years of hardware engineering or related experience; OR Master's degree in the same fields with 2+ years' experience; OR PhD in the same fields with 1+ year of experience. Preferred qualifications also list Bachelor's/Master's/PhD in Electrical, Electronics, or Computer Engineering.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.