Infra Design Verification Senior Engineer
QualcommJob Title
Infra Design Verification Senior Engineer
Role Summary
Join a hardware verification team responsible for implementing UVM-based verification environments and ensuring correctness of high-speed interconnects and subsystem integrations. The role works closely with RTL designers, architects, validation, and bring-up teams to drive verification closure for SoC/subsystem designs.
Experience Level
Senior. Preferred: 3+ years of ASIC/Subsystem/SoC verification experience; the team expects experienced verification engineers able to lead verification efforts and mentor junior engineers.
Responsibilities
Primary verification and integration responsibilities for high-speed interconnects and subsystem components.
- Develop and maintain UVM-based verification environments for protocols such as PCIe, CXL, AXI, and CHI.
- Create and execute verification plans, functional coverage, and regression suites at block and top levels.
- Implement and enhance scoreboards, agents, monitors, and sequences; drive coverage convergence.
- Use third-party VIPs (Synopsys, Mentor) for protocol compliance and integration.
- Collaborate with RTL designers, architects, and validation teams to debug RTL and gate-level failures and ensure design correctness.
- Integrate and validate SMMU and Coresight components within subsystem environments.
- Contribute to performance, power, and cost optimization considerations during verification; apply power-aware verification practices.
- Mentor junior engineers and improve verification methodologies and flows.
Requirements
Must-have technical skills and tools for this role; preferred items listed separately.
- Must-have: Strong proficiency in SystemVerilog, UVM, and verification methodologies (coverage-driven and assertion-based verification).
- Must-have: Deep protocol knowledge: PCIe (Gen3–Gen6), CXL (1.1/2.0/3.0), AXI/CHI, and SMMU/Coresight architectures.
- Must-have: Experience with Synopsys/Mentor VIPs and assertion languages (SVA); experience in random constraint-based testing.
- Must-have: Scripting proficiency for automation (Python, Perl, or Tcl).
- Must-have: Experience debugging RTL and gate-level simulations and driving coverage closure.
- Nice-to-have: Knowledge of UPF (power-aware verification), formal verification, and performance/power optimization techniques.
- Nice-to-have: Experience with peripheral protocols (USB, Ethernet) and post-silicon validation / lab bring-up.
Education Requirements
Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field (typically with 2+ years hardware/verification experience); OR Master's degree in those fields (typically with 1+ year experience); OR PhD in those fields. Preferred qualifications also list Bachelor's/Master's/Ph.D. in Electrical, Electronics, or Computer Engineering.
About the Company
Company: Qualcomm
Headquarters: San Diego, California, United States
Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.
