Infra Design Verification Senior Engineer

Job Title

Infra Design Verification Senior Engineer

Role Summary

Join a hardware verification team responsible for functional verification of high-speed interconnects and subsystems on SoC and subsystem designs. The engineer will develop UVM-based testbenches, execute verification plans, close coverage, and collaborate with RTL designers and validation teams to ensure design correctness.

Experience Level

Senior-level. Preferred experience range: 3–6 years in ASIC/SoC verification; minimum listed experience: 2+ years with a Bachelor’s or 1+ year with a Master’s (PhD also accepted).

Responsibilities

Primary responsibilities focus on verification planning, environment development, and coverage closure for high-speed protocols and subsystem integration.

• Develop and maintain UVM-based verification environments for PCIe, CXL, AXI and related protocols.
• Create and execute verification plans at block and top-level; implement functional coverage and regression suites.
• Implement and improve scoreboards, agents, monitors, and sequences.
• Use third-party VIPs (Synopsys, Mentor) and integrate protocol VIP for compliance testing.
• Perform assertion-based verification, debug RTL and gate-level simulation failures, and drive coverage convergence.
• Integrate and validate SMMU and Coresight components within subsystem environments.
• Collaborate with architects, RTL designers, and validation teams to derive verification strategies.
• Mentor junior engineers and contribute to verification methodology improvements.

Requirements

Must-have technical skills and experience; preferred items listed separately.

• Strong proficiency in SystemVerilog and UVM verification methodologies.
• Deep protocol knowledge: PCIe (Gen3–Gen6), CXL (1.1–3.0), AXI/CHI.
• Experience with assertion-based verification (SVA), coverage-driven testing, and random constraint-based verification.
• Familiarity with Synopsys/Mentor VIPs and using third-party VIPs for protocol compliance.
• Scripting for automation: Python, Perl, and/or Tcl.
• Experience debugging RTL and gate-level simulation failures and driving closure through coverage and assertions.
• Knowledge of power-aware verification (UPF), formal verification concepts, and performance/power optimization.
• Ability to work in cross-functional teams and communicate verification status and risks.
• Nice-to-have: exposure to post-silicon validation, lab bring-up, or peripheral protocols (USB, Ethernet).

Education Requirements

Minimum qualifications list one of: Bachelor’s degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field (with 2+ years hardware engineering experience); OR Master’s degree in those fields (with 1+ year experience); OR PhD in a related field. Preferred qualifications reiterate Bachelor’s/Master’s/PhD in Electrical, Electronics, or Computer Engineering.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.