Implementation Engineer, Staff

Job Title

Implementation Engineer, Staff

Role Summary

Lead and grow a technical implementation team working on the Display Sub-System implementation flow. Responsible for delivery of signoff-quality netlists, timing closure, low-power intent, and process improvements across multiple, time-critical projects.

Experience Level

Senior level. The posting indicates a typical staff-level experience range of 9–13+ years; minimum-qualification alternatives are provided (see Education Requirements).

Responsibilities

Accountable for end-to-end implementation tasks and team execution for complex display subsystem blocks.

• Lead and manage multiple time-critical implementation projects and coordinate cross-functional stakeholders.
• Develop and deliver signoff-quality synthesis constraints and power-intent (UPF) constraints.
• Perform synthesis, logic equivalence checks (LEC), low-power checks, memory BIST insertion, and constraints validation.
• Run and analyze RTL lint, CLP, MEMBIST, and DFT DRC as required.
• Develop and maintain TCL scripts; debug synthesis and implementation runs.
• Handle ECOs and support formal verification to maintain high quality metrics.
• Drive optimizations in area, power and performance and improve execution efficiency and flows.
• Collaborate with design, DFT and physical design teams for netlist delivery and timing closure.

Requirements

Must-have technical experience and skills for the implementation lead role.

• Strong understanding of physical synthesis and synthesis methodologies using industry-standard tools.
• Proven experience writing timing constraints, performing STA, and achieving timing closure for multi-clock domain designs.
• Familiarity with MCMM synthesis and multi-clock optimization techniques.
• Knowledge of low-power implementation techniques and experience applying UPF-based flows.
• Hands-on experience with Synopsys DCG/Genus/Fusion Compiler and Synopsys PrimeTime for constraint development and timing signoff.
• Hands-on experience with Cadence Conformal LEC and Conformal Low Power (UPF-related flows).
• Scripting skills in TCL and at least one of Perl or Python for automation and debug.
• Experience with ECO flows, memory BIST insertion, and LEC-based verification.
• Strong leadership, communication, and cross-functional collaboration skills to grow and mentor the team.
• Nice-to-have: prior RTL development or physical design experience; familiarity with additional power-optimization techniques such as clock gating.

Education Requirements

The posting requests a Bachelor's, Master's, or PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field. It provides alternative minimum experience thresholds: Bachelor's +4 years, Master's +3 years, or PhD +2 years of relevant hardware engineering experience. The role also indicates a typical staff-level expectation of ~9–13+ years of experience.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.