IC Design Engineer (STA/Synthesis)
BroadcomJob Title
IC Design Engineer (STA/Synthesis)
Role Summary
Lead STA/Synthesis engineer responsible for timing constraint development, static timing analysis, synthesis, static audits, and timing closure for mission‑critical IP and ASIC blocks in advanced technology nodes. Works within ASIC/SoC design teams to define signoff methodologies and drive timing closure.
Experience Level
Senior-level role. The position requires substantial industry experience and responsibility for timing signoff and closure across complex designs.
Responsibilities
Primary duties include timing analysis, synthesis and audits, constraint development, and driving timing closure.
- Develop and validate timing constraints for complex hierarchical SoC designs.
- Perform static timing analysis (STA) using industry tools (e.g., PrimeTime, Tempus, TCM).
- Run synthesis flows and perform static audits (CDC, RDC, Low Power, logical equivalence) for high‑speed digital and mixed‑signal blocks.
- Define and implement timing signoff methodologies, including corners, derates, and uncertainties.
- Conduct pre‑route timing checks and QoR analysis; generate timing ECOs.
- Automate timing and synthesis flows using scripting (Tcl, Perl) and internal tooling.
- Provide guidance on clock tree synthesis and optimization for power and timing.
- Ensure compliance with timing signoff checklists and criteria; drive closure for complex IP/ASIC blocks.
Requirements
Must-have technical skills, tools, and professional abilities; nice-to-have items noted.
- Must-have: Proven experience with STA tools (PrimeTime, Tempus, TCM) and synthesis/audit tools (DC‑T, Genus, Fishtail, VCLP, Formality).
- Must-have: Strong experience in timing constraint development, timing signoff, and timing closure on complex designs in advanced nodes.
- Must-have: Experience performing CDC, RDC, low‑power, and equivalence audits.
- Must-have: Proficiency in scripting (Tcl, Perl) to automate analysis and synthesis flows.
- Must-have: Familiarity with ASIC design flows (RTL, place‑and‑route) and clock tree planning/implementation.
- Must-have: Strong problem solving, attention to detail, and ability to work independently across geographies.
- Nice-to-have: Direct RTL/design experience; prior work on high‑complexity silicon and advanced technology nodes.
Education Requirements
Posting specifies degree-plus-experience thresholds: Bachelor's degree with 12+ years related experience, Master's degree with 10+ years related experience, or PhD with 7+ years related experience. Post‑graduate coursework is noted as highly desirable. The posting does not list specific fields of study or certifications.
About the Company
Company: Broadcom
Headquarters: Irvine, California, United States
Broadcom is a global technology leader that designs, develops, and supplies a wide range of semiconductor and infrastructure software solutions. The company is known for its innovations in wireless and broadband communications, enabling a connected world.
