IC Design Engineer (DFT)

Job Title

IC Design Engineer (DFT)

Role Summary

Work on ASIC design-for-test (DFT) implementation and verification for CMOS cell-based ASICs. The role covers DFT architecture, implementation, simulation, timing verification, and test bring-up across advanced nodes (including 5nm/3nm).

Experience Level

Mid-level — requires 5+ years of related DFT/ASIC experience.

Responsibilities

Primary responsibilities include design and verification of DFT features and supporting test bring-up.

• Participate in chip-level DFT architecture definition.
• Implement DFT schemes: scan, boundary scan, MBIST, Logic BIST, and SSN.
• Verify DFT logic and test patterns via simulation.
• Perform static timing analysis for test modes.
• Support ATE bring-up and debug DFT patterns on ATE.
• Support vector generation and post-prototype test debug.

Requirements

Must-have technical skills and tools experience.

• Strong understanding of DFT methodologies: BIST, SCAN, JTAG, ATPG.
• Familiarity with Mentor or Synopsys DFT flows and tools.
• Experience developing synthesis and STA constraints.
• Multi-mode, multi-corner STA experience and understanding of sign-off checks.

Nice-to-have:

• Experience with advanced process nodes (5nm/3nm).
• Hands‑on experience with ATE pattern debug and vector generation.

Education Requirements

Either a Bachelor's or Master's degree is required; Preferred: MS in Microelectronics or a related discipline. 5+ years of related experience is also required.

About the Company

Company: Broadcom

Headquarters: Irvine, California, United States

Broadcom is a global technology leader that designs, develops, and supplies a wide range of semiconductor and infrastructure software solutions. The company is known for its innovations in wireless and broadband communications, enabling a connected world.