IC Design Engineer
Member of the ASIC Implementation team responsible for synthesis and timing closure for complex SoC designs. Lead synthesis, static timing analysis, constraints development, and timing-closure efforts while coordinating with RTL, PNR, IP, and library teams and improving synthesis/STA/low-power methodologies and flows.
Senior β target candidates with senior-level IC design and timing-closure experience (see Education Requirements for years-of-experience guidance).
Primary responsibilities include synthesis, timing closure, constraints generation, and cross-team coordination.
Must-have technical skills and experience.
Bachelor's degree in Engineering with 12+ years of related experience, or Master's degree in Engineering with 10+ years of related experience.
Company: Broadcom
Headquarters: Irvine, California, United States
Broadcom is a global technology leader that designs, develops, and supplies a wide range of semiconductor and infrastructure software solutions. The company is known for its innovations in wireless and broadband communications, enabling a connected world.
