HSIO Validation Lead — Silicon Co-Design

Job Title

HSIO Validation Lead — Silicon Co-Design

Role Summary

Owner for post-silicon bring-up, characterization, validation, and debug of high-speed I/O (HSIO) interfaces across NVIDIA GPUs, CPUs, and SoCs. Work spans protocol behavior, signal integrity, firmware, drivers, platform topology, and silicon marginalities from first power-on to production readiness.

This role sits in the Silicon Co-Design group, coordinating technical decisions across architecture, design, firmware, drivers, ATE, and product teams while improving validation methodology and coverage.

Experience Level

Senior — typically 8+ years in silicon validation, HSIO bring-up, or high-speed interface debug on real hardware.

Responsibilities

Lead validation and debug activities that determine production readiness and field quality for high-speed interfaces.

• Own post-silicon bring-up, characterization, validation, and debug of PCIe, NVLink, C2C, and other HSIO interfaces through production readiness.
• Drive root-cause analysis across protocol behavior, signal integrity, firmware/drivers, platform topology, and silicon marginalities; own fixes through verification.
• Define validation strategy: test coverage, debug priorities, margining methodology, and stress criteria per program.
• Design and build AI-driven automation for debug triage, data pipelines, and analysis flows to reduce cycle time while managing risk.
• Ensure interoperability across ecosystem components: retimers, switches, accelerators, CPUs, GPUs, and multi-device topologies.
• Provide data-driven analysis to align architecture, design, firmware, test, and product teams and inform technical decisions.
• Translate silicon findings into methodology and coverage improvements for future products.

Requirements

Key technical skills, tools, and hands-on experience required or strongly preferred.

• 8+ years of practical experience in silicon validation, HSIO bring-up, or high-speed interface debug on physical hardware.
• Deep protocol expertise in PCIe, NVLink, CXL, C2C, Ethernet, USB, or similar high-speed interfaces.
• Strong signal integrity fundamentals: SERDES behavior, link training, equalization, clocking, reset, power management, and board/system interactions.
• Hands-on lab experience with oscilloscopes, BERTs, protocol analyzers, logic analyzers, exercisers, ATE, and silicon debug tools.
• Proven ability to debug across the full stack: hardware, firmware, drivers, and platform design.
• Statistical proficiency to interpret marginal distributions and guide investigation and margining decisions.
• Experience defining validation strategy, test coverage, and margining methodology.
• Nice-to-have: experience building or deploying AI-driven flows for HSIO debug or failure triage.
• Nice-to-have: track record of driving customer-critical or production-blocking HSIO failures to resolution and/or setting technical direction across a validation organization.

Education Requirements

BS or MS in Electrical Engineering, Computer Engineering, or Systems Engineering, or equivalent practical experience in the lab.

About the Company

Company: NVIDIA

Headquarters: Santa Clara, California, USA

NVIDIA is a global leader in accelerated computing, renowned for its innovative solutions in AI and digital twins that transform diverse industries. The company specializes in networking technologies, providing end-to-end InfiniBand and Ethernet solutions for servers and storage that optimize performance and scalability. NVIDIA serves sectors such as high-performance computing, enterprise data centers, and cloud computing, constantly reinventing its products and services to stay ahead in the market.