High Speed IO Validation Engineer

Job Title

High Speed IO Validation Engineer

Role Summary

Own characterization and qualification of high-speed I/Os (PCIe, NVLink, NVLink-C2C, UCIe, USB, UFS, Ethernet) from die through package and board on NVIDIA GPUs, CPUs, and SoCs. Drive validation, debug, and margin analysis across silicon, package, board, firmware, and driver to ensure link margin, BER, power per lane, and production readiness.

Experience Level

Senior — typically requires 8+ years of post-silicon HSIO validation, characterization, or closely related experience.

Responsibilities

Lead end-to-end HSIO validation efforts and deliver silicon- and system-level validation artifacts that inform productization.

• Plan and execute HSIO validation from bring-up through corner qualification, stress, and productization across PVT, board, cable/connector, thermal, and firmware variables.
• Design and run DOE, jitter sweeps, BER margining, eye analysis, and structured tests to quantify link margin and reliability.
• Drive power characterization and optimization across IO interconnects under workload-representative stimuli and analyze trade-offs across V/F, lane config, and protocol state.
• Perform root-cause analysis for complex HSIO failures across silicon, package, board, firmware, driver, and system; convert rack-observed failures into silicon/board reproducers.
• Assess manufacturing and yield implications of HSIO margin distributions and recommend binning or design adjustments.
• Develop and improve validation methodologies, automation frameworks, and margin-tracking infrastructure.

Requirements

Must-have:

• 8+ years of post-silicon HSIO validation, characterization, or closely related discipline.
• Deep understanding of high-speed serial protocols (PCIe Gen5+, NVLink, NVLink-C2C, UCIe, CXL) and SERDES fundamentals (link training, equalization, electrical characterization).
• Strong signal integrity and power integrity fundamentals: S-parameters, eye diagrams, channel margin, crosstalk, return loss, PDN noise, and jitter decomposition.
• Validation experience across silicon and platform boundaries (CoWoS/interposer/substrate, board) and translating rack-environment effects into silicon/board characterization.
• Hands-on experience with lab instrumentation (DSO, BERT, VNA, protocol/logic analyzers, TDR), DOE/shmoo/margin-trending, and Python-based test automation.
• Proven ability to drive cross-functional debug across chip, package, board, firmware, driver, and system teams.

Nice-to-have:

• Experience with PCIe Gen5/Gen6 or NVLink validation on production silicon (link training, equalization tuning, BER margining, compliance debug).
• Background in SERDES, mixed-signal, or analog circuit design enabling Sim-to-Si correlation and silicon-side fixes.
• Track record of translating rack conditions (thermal, connector reliability, neighbor noise) into silicon/board characterization.
• Familiarity with AI productivity tools for log triage, regression analysis, scripting, and reporting.

Education Requirements

BS or MS in Electrical Engineering or Computer Engineering (or equivalent practical experience). The posting explicitly allows equivalent practical experience in place of a degree.

About the Company

Company: NVIDIA

Headquarters: Santa Clara, California, USA

NVIDIA is a global leader in accelerated computing, renowned for its innovative solutions in AI and digital twins that transform diverse industries. The company specializes in networking technologies, providing end-to-end InfiniBand and Ethernet solutions for servers and storage that optimize performance and scalability. NVIDIA serves sectors such as high-performance computing, enterprise data centers, and cloud computing, constantly reinventing its products and services to stay ahead in the market.