High Speed Interface Protocols, Principal AE

Job Title

Principal Applications Engineer — High Speed Interface Protocols

Role Summary

Architect and demonstrate high-speed interface solutions for customers using Cadence Serdes PHY and controller IP. This is a customer-facing pre-sales and technical account role within the Serdes Applications team that combines technical leadership, solution architecture, and internal process improvement to grow the IP business.

Experience Level

Senior level. Typical expectation: MS in EE/CE (or equivalent) with ~10+ years relevant experience, or BS in EE/CE (or equivalent) with ~15+ years relevant experience.

Responsibilities

Primary responsibilities include technical pre-sales, customer enablement, and cross-functional collaboration.

• Provide technical pre-sales and configuration of high-speed interface IP (PCIe, CXL, Ethernet PHY & controllers).
• Present product capabilities and demonstrate IP performance to prospective customers and at events.
• Act as product expert for digital controller and PHY IPs and related protocols.
• Collaborate with sales, marketing, and R&D to secure opportunities and define solutions.
• Deliver quick-turn technical support to customers, field teams, architects, and designers.
• Author application notes and technical articles for internal and external audiences.
• Define and lead initiatives to improve team processes and productivity.
• Occasional travel to customer sites as required.

Requirements

Must-have technical skills and professional abilities.

• Deep knowledge of one or more high-speed interface protocols: PCIe, CXL, UCIe, Ethernet, USB, MIPI, 224G, 112G.
• Strong understanding of PHY and/or controller architectures for high-speed interfaces.
• Proven ability to manage pre-sales technical accounts and lead customer engagements.
• Excellent presentation and verbal/written communication skills.

Nice-to-have:

• Lab validation and demo setup experience.
• Experience in controller and/or PHY verification.
• Knowledge of AXI and PIPE interface protocols.
• Working knowledge of high-speed interface PHY implementation and validation.

Education Requirements

BS in Electrical Engineering (EE), Computer Engineering (CE) or related field with ~15+ years of relevant work experience, or MS in EE/CE (or equivalent) with ~10+ years of relevant work experience. Equivalent practical experience may be considered.

About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.