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High Performance DSP Core Implementation (Synthesis) Engineer

Qualcomm
September 19, 2026
Full-time
On-site
Noida, Uttar Pradesh, India
Physical Design Jobs, Level - Mid-Career

Job Title

High Performance DSP Core Implementation (Synthesis) Engineer

Role Summary

Work on physical synthesis and implementation for high-performance DSP cores and related IP blocks within SoC designs. Deliver timing-closed netlists, implement low-power optimizations, and collaborate with design, DFT and physical design teams to meet performance, power and quality targets.

Experience Level

Mid-level - typically requires at least 2 years of hands-on experience in synthesis and equivalence checking.

Responsibilities

Primary responsibilities focus on synthesis, timing closure and netlist delivery for multi-clock domain DSP designs.

  • Define and execute physical synthesis flows using industry tools for QoR and timing closure.
  • Write and validate timing constraints for synthesis and static timing analysis (STA).
  • Perform timing closure and pipelining optimizations across multiple clock domains.
  • Implement low-power techniques during synthesis using UPF and clock gating strategies.
  • Manage MCMM synthesis and multi-corner/multi-mode optimizations.
  • Work with design, DFT and PD teams to deliver netlists and validate timing constraints.
  • Handle ECOs, perform formal/LEC verification and maintain design quality metrics.
  • Automate flows and report results using scripts and regression frameworks.

Requirements

Must-have skills and experience for immediate contribution; nice-to-have items follow.

  • Must have: 2+ years hands-on experience in synthesis and LEC.
  • Must have: Proficiency in Python and Tcl scripting for flow automation.
  • Must have: Experience with synthesis tools such as Fusion Compiler or Genus.
  • Must have: Proficient in front-end VLSI design: Verilog/VHDL, synthesis QoR optimization and equivalence checking.
  • Must have: Experience with timing closure for multi-clock domain designs and STA methodologies.
  • Must have: Familiarity with low-power implementation flows (UPF) and clock-gating techniques.
  • Nice to have: Experience with LP signoff tools, formal verification flows, and configuration management/regression practices.
  • Nice to have: Prior experience coordinating with DFT and PD teams on netlist delivery and ECO handling.

Education Requirements

Bachelor's degree in Science, Engineering, or a related field (as listed in minimum qualifications).


About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.

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Date Posted: 2026-09-19