Head - SoC Physical Design Manager

Job Title

Head - SoC Physical Design Manager

Role Summary

Technical and people leadership role to lead NXP's Physical Design organization responsible for implementation and signoff of advanced mixed-signal SoCs. The role spans early physical architecture and floorplanning through place & route, STA, power and timing closure, physical verification and tape-out.

The manager will build and develop a high‑performance engineering team, establish common methodologies and best practices, and collaborate across multiple organizations to improve implementation flows and product quality.

Experience Level

Senior - leadership role. No specific years-of-experience requirement stated in the posting.

Responsibilities

The role combines organizational leadership with hands-on technical direction for complex IC and mixed-signal SoC implementation and signoff.

• Lead, develop and grow a team of Physical Design, STA and signoff engineers; set priorities and accountability.
• Establish technical direction, engineering standards and a culture of technical excellence and continuous improvement.
• Coach and mentor technical leaders and engineers to build technical depth and future leadership capability.
• Plan resources and capabilities across multiple development programs.
• Own Physical Design strategy and execution for complex IC and mixed-signal SoC developments.
• Lead floorplanning, partitioning, power planning, placement, clock-tree implementation, routing and physical optimization.
• Drive Static Timing Analysis and timing closure in complex multi-mode, multi-corner environments.
• Lead implementation and verification of power-management architectures including multiple voltage domains, power gating, level shifting and always-on domains.
• Ensure robust physical verification and signoff (DRC, LVS) and tape-out readiness.
• Collaborate with peer teams, EDA, methodology, technology, library and IP teams to standardize flows and adopt improvements across the company.

Requirements

Must-have technical and leadership qualifications for the role.

• Proven experience in advanced IC/SoC Physical Design with multiple successful tape-outs and high-volume product ramps.
• Deep technical knowledge of place & route, STA, timing closure, packaging, physical signoff, IR-drop, electromigration, signal and power integrity, and reliability for low-power designs with complex power management.
• Strong understanding of interactions among architecture, RTL, synthesis, DFT, physical design, analog design, packaging and silicon validation.
• Experience improving and industrializing EDA methodologies, automation and design flows.
• Proven experience leading, mentoring and developing engineering teams and technical leaders.
• Ability to influence technical decisions across organizations and to build alignment between engineering teams.
• Strong communication skills and ability to translate complex engineering issues into clear technical and program decisions.
• Nice-to-have: experience with Physical Design of secure products; experience collaborating across multiple sites or business groups.

Education Requirements

Not specified.

About the Company

Company: NXP Semiconductors

Headquarters: Nijmegen, Netherlands

NXP Semiconductors N.V. is a global semiconductor company that provides High Performance Mixed Signal and Standard Product solutions. With over 45,000 employees and operations in more than 35 countries, NXP is a leader in secure connectivity solutions for embedded applications, catering to automotive, industrial IoT, mobile, and communication infrastructure markets. The company is committed to innovation and sustainability, advancing a smarter, safer, and more sustainable world through technology.