HBM SoC Physical Design Engineer

Job Title

HBM SoC Physical Design Engineer

Role Summary

As a SoC Physical Design Engineer in the Heterogeneous Integration Group (HIG), you will implement advanced HBM SoC logic/base die designs from netlist to GDSII. You will collaborate with RTL, verification, DFT, IP providers, packaging, and manufacturing teams to deliver target performance, power, area (PPA) and signoff-quality deliverables.

Experience Level

Senior - minimum 10 years of relevant SoC physical design experience preferred.

Responsibilities

Primary responsibilities include physical implementation, timing closure, signoff readiness, and cross-functional coordination.

• Lead physical implementation for SoC blocks and/or top level: floorplanning, placement, CTS, routing, and PPA-driven optimization.
• Drive timing closure across multi-mode/multi-corner scenarios; coordinate with RTL, architecture, and STA/signoff teams.
• Integrate complex IP (controllers, microcontrollers, NOC, interfaces, MBIST/DFT logic, PHY-adjacent logic) with robust timing and power integrity.
• Perform or coordinate physical signoff activities: DRC/LVS, IR drop/EM, parasitic extraction, and timing signoff remediation.
• Partner with DFT teams to ensure scan/MBIST requirements are physically realizable without compromising PPA or schedule.
• Collaborate with packaging, assembly, test, probe, and manufacturing to ensure manufacturability and quality of builds.
• Support tape-out execution (checklists, ECO flows, signoff reviews) and contribute to post-silicon debug by correlating silicon behavior with PD/STA/power analysis.
• Identify flow gaps and improve productivity through scripting, automation, and methodology development.

Requirements

Must-have technical skills and experience; preferred items noted.

• Proven SoC physical design experience implementing designs from netlist to GDSII on advanced process nodes.
• Proficiency with industry EDA tools (for example, Cadence Innovus/Tempus, Synopsys ICC2/PrimeTime, Siemens Calibre or equivalent).
• Solid understanding of STA fundamentals: clocking, constraints (SDC), and common closure techniques (buffering, path shaping, useful skew).
• Experience with power intent and power delivery considerations (UPF/CPF concepts, power grid planning, power gating implications).
• Familiarity with physical verification and signoff concepts: DRC, LVS, ERC, parasitic extraction awareness, and signoff handoff quality.
• Strong collaboration skills across RTL, verification, DFT, IP providers, packaging, and manufacturing teams.
• Nice-to-have: experience with HBM/DRAM-adjacent SoC designs and prior mentoring of early-career engineers.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field is preferred.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.