HBM SoC Physical Design Engineer

Job Title

HBM SoC Physical Design Engineer

Role Summary

As a SoC Physical Design Engineer in the Heterogeneous Integration Group (HIG), you will implement advanced HBM SoC logic/base-die designs from netlist to GDSII. You will collaborate with RTL design, verification, DFT, IP providers, packaging, and manufacturing teams to meet performance, power, area (PPA) targets and produce signoff-ready deliverables.

Experience Level

Senior — this role targets experienced engineers; the posting indicates a preference for candidates with a minimum of 10 years of related experience.

Responsibilities

Primary responsibilities include physical implementation, signoff preparation, and cross-functional integration for HBM-capable SoCs.

• Own physical implementation for SoC blocks and/or top-level: floorplanning, placement, CTS, routing, and physical optimization to meet PPA targets.
• Drive timing closure across multi-mode/multi-corner (MMMC) scenarios; work with RTL, architecture, and STA/signoff teams.
• Integrate and implement complex IP (controllers, microcontrollers, NOC, interfaces, MBIST/DFT logic, PHY-adjacent logic) with attention to timing and power integrity.
• Perform/coordinate physical signoff activities including DRC/LVS, IR drop/EM analysis, and timing signoff; address violations efficiently.
• Partner with DFT teams to ensure scan/MBIST physical realization without compromising PPA or schedule.
• Collaborate with packaging, assembly, test, probe, and manufacturing to ensure manufacturability and quality for builds.
• Support tape-out execution (checklists, ECO flows, signoff reviews) and assist post-silicon debug by correlating silicon to PD/STA/power analysis.
• Identify flow gaps and improve productivity through scripting, automation, and methodology development.

Requirements

Must-have technical skills and experience for successful performance in this role.

• Strong experience in SoC physical design implementation from netlist to GDSII on advanced process nodes and complex designs.
• Proficiency with industry EDA tools (examples: Cadence Innovus/Tempus, Synopsys ICC2/PrimeTime, Siemens Calibre or equivalent).
• Solid understanding of STA fundamentals, clocking, constraints (SDC), and common closure techniques (buffering, path shaping, useful skew, etc.).
• Experience with power intent and power delivery concepts (UPF/CPF, power grid planning, power gating implications).
• Familiarity with physical verification and signoff concepts: DRC, LVS, ERC, parasitic extraction awareness, and signoff handoff expectations.
• Experience coordinating cross-functional deliverables with RTL, verification, packaging, test, and manufacturing teams.
• Ability to develop scripts and automation to improve design flow productivity and repeatability.

Nice-to-have:

• Experience with HBM/DRAM-adjacent SoC designs or memory-subsystem-heavy SoCs.
• Proven ability to mentor and develop early-career engineers.
• Minimum 10 years of related industry experience (listed as preferred by the employer).

Education Requirements

Bachelor’s or master’s degree in Electrical Engineering, Computer Engineering, or a related field (as stated in the posting).

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.