HBM SoC Physical Design Engineer

Job Title

HBM SoC Physical Design Engineer

Role Summary

Hands-on SoC Physical Design Engineer in the Heterogeneous Integration Group responsible for implementing advanced HBM SoC logic/base die designs from netlist to GDSII. Collaborate with RTL, verification, DFT, IP providers, packaging, and manufacturing to meet performance, power, area (PPA) targets and signoff requirements. Support integration of AI-driven tools and automation into physical design flows.

Experience Level

Level - Mid-Career. Minimum 3 years of related experience is listed as preferred.

Responsibilities

Key technical responsibilities for block and top-level physical implementation and delivery.

• Own physical implementation: floor-planning, placement, CTS, routing, and physical optimization to meet PPA targets.
• Drive timing closure (setup/hold) across multi-mode/multi-corner (MMMC) scenarios; coordinate with RTL, architecture, and STA/signoff teams.
• Integrate and implement complex IP (controllers, NOC, interfaces, MBIST/DFT logic, PHY-adjacent logic) with attention to timing and power integrity.
• Perform or coordinate physical signoff activities: DRC/LVS, IR drop/EM, parasitic extraction awareness, and timing signoff.
• Partner with DFT to ensure scan/MBIST requirements are physically realizable without compromising PPA or schedule.
• Work with packaging, assembly, test, probe, and manufacturing to ensure manufacturability and build quality.
• Support tape-out execution (checklists, ECO flows, signoff reviews) and contribute to post-silicon debug via PD/STA/power analysis.
• Identify flow gaps and improve productivity through scripting, automation, and methodology development; enable AI-assisted workflows where applicable.

Requirements

Required technical skills and tools for immediate contribution. Preferred items noted separately.

• Must-have: Strong experience in SoC physical design implementation from netlist to GDSII on advanced process nodes and complex designs.
• Must-have: Proficiency with industry EDA tools (examples: Cadence Innovus/Tempus, Synopsys ICC2/PrimeTime, Siemens Calibre or equivalents).
• Must-have: Solid understanding of STA fundamentals, clocking, SDC constraints, and common closure techniques (buffering, path shaping, useful skew, etc.).
• Must-have: Experience with power intent and power delivery planning (UPF/CPF concepts, power grid planning, power gating implications).
• Must-have: Familiarity with physical verification/signoff concepts: DRC, LVS, ERC, parasitic extraction awareness, and signoff-quality handoffs.
• Nice-to-have: Experience with HBM/DRAM-adjacent SoC designs or memory-subsystem-heavy SoCs; experience mentoring junior engineers; exposure to Agentic AI or willingness to adopt AI-enabled workflows.

Education Requirements

Bachelor's or master’s degree in Electrical Engineering, Computer Engineering, or a related field.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.