HBM SoC Physical Design Engineer

Job Title

HBM SoC Physical Design Engineer

Role Summary

As a SoC Physical Design Engineer in the Heterogeneous Integration Group (HIG), you will implement advanced HBM SoC logic/base die designs from netlist to GDSII and own block or top-level physical implementation across product generations. You will collaborate with RTL, verification, DFT, IP providers, packaging, and manufacturing teams to meet performance, power, area (PPA) and signoff requirements.

Experience Level

Senior — minimum 10 years of relevant experience (per job posting).

Responsibilities

Primary responsibilities include physical implementation, signoff, and cross-team integration to deliver tape-out-ready SoC designs.

• Perform floor-planning, placement, clock tree synthesis, routing, and physical optimizations to meet PPA targets.
• Drive timing closure across multi-mode/multi-corner scenarios; coordinate with RTL, architecture, and STA/signoff teams.
• Integrate complex IP (controllers, NOCs, interfaces, DFT logic, PHY-adjacent logic) ensuring robust physical and timing integration.
• Execute or coordinate physical signoff (DRC/LVS, IR drop/EM analysis, timing signoff) and address violations.
• Collaborate with DFT, packaging, assembly, test, probe, and manufacturing to ensure manufacturability and quality.
• Support tape-out activities (checklists, ECO flows, signoff reviews) and post-silicon debug by correlating silicon behavior with PD/STA/power analysis.
• Identify flow gaps and improve productivity through scripting, automation, and methodology development.

Requirements

Required technical skills and experience; preferred items noted separately.

• Proven experience in SoC physical design implementation from netlist to GDSII on advanced process nodes and complex designs.
• Proficiency with industry EDA tools such as Cadence Innovus/Tempus, Synopsys ICC2/PrimeTime, and Siemens Calibre (or equivalents).
• Strong understanding of static timing analysis fundamentals, clocking, SDC constraints, and common closure techniques (buffering, path shaping, useful skew).
• Experience with power-intent concepts and power delivery planning (UPF/CPF, power grid, power gating implications).
• Familiarity with physical verification and signoff concepts: DRC, LVS, ERC, parasitic extraction awareness, and signoff handoff quality.
• Ability to work collaboratively across RTL, DFT, packaging, and manufacturing teams and to mentor junior engineers (preferred).
• Experience with HBM or DRAM-adjacent SoC designs and memory-heavy subsystems is a plus.

Education Requirements

Bachelors or masters degree in Electrical Engineering, Computer Engineering, or a related field.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.