Hardware & Silicon Validation Principal Engineer

Job Title

Hardware & Silicon Validation Principal Engineer

Role Summary

Principal engineer on the Custom Cloud Solutions (CCS) Hardware Validation Group responsible for end-to-end validation of high-performance ASICs and SoCs (including SerDes, memory subsystems, PCIe, Ethernet, storage and platform-level testing) from early bring-up through production readiness.

Work in advanced hardware labs to develop validation strategies, electrical characterization, compliance testing, automation, and customer-facing debug for next-generation data center and accelerator products.

Experience Level

Senior / Principal level. Typical background: Bachelor’s + 8+ years industry experience, or Master’s/PhD + 5+ years; 5–7+ years of direct SerDes characterization or signal-integrity experience is expected.

Responsibilities

Lead and execute validation and qualification activities for SerDes and system interfaces; develop automation and lead cross-functional technical efforts.

• Lead electrical characterization, compliance testing, and debug for SerDes IP targeting IEEE 802.3ck/dj and PCIe Gen5/Gen6 at 112G/224G.
• Develop and maintain automated validation methodologies, regression frameworks, and compliance test plans.
• Perform signal integrity analysis and correlate pre-silicon models/simulations with lab measurements.
• Define and own end-to-end SerDes validation strategy and production readiness sign-off for assigned programs.
• Provide technical support and on-site debug for strategic customers; present performance findings to customers and leadership.
• Manage test-equipment CAPEX and ensure measurement infrastructure readiness.
• Mentor and develop staff-level and junior engineers in SI measurement and test automation practices.
• Contribute to high-speed board design reviews, channel extraction, and test infrastructure development.
• Author validation reports, application notes, and best-known-methods documents; represent the company in industry technical forums.

Requirements

Must-have technical skills and experience for successful performance in this role.

• 5–7+ years of direct SerDes characterization, design, or signal integrity engineering experience.
• Deep expertise in Ethernet (IEEE 802.3ck/dj) electrical compliance and/or PCIe Gen5/Gen6 validation.
• Strong knowledge of signal integrity: channel modeling, S-parameter analysis, and equalization (CTLE, DFE, FFE).
• Hands-on experience with SerDes test equipment: real-time/sampling oscilloscopes, BERTs, VNAs, pattern generators, protocol analyzers.
• Proficiency in Python for test automation, data analysis, and regression infrastructure.
• Proven ability to lead technical projects, drive closure on discrepancies, and mentor engineers.
• Experience correlating pre-silicon simulations with post-silicon measurements.
• Excellent verbal and written communication skills for customer and executive interactions.
• Nice-to-have: experience with high-speed PCB design, SI simulation tools (HFSS, ADS, Sigrity), and active participation or familiarity with IEEE 802.3 or PCI-SIG.

Education Requirements

Bachelor's degree in Computer Science, Electrical Engineering, or a related field (posted requirement: Bachelor’s + 8+ years); or Master’s degree and/or PhD in Computer Science, Electrical Engineering, or a related discipline with 5+ years of professional experience. (No specific certifications listed.)

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.