Hardware Engineering Architect

Job Title

Hardware Engineering Architect

Role Summary

Senior engineering role on the R&D circuits team responsible for signal and power integrity (SIPI) analysis for DDR and HBM PHYs. The position leads interconnect and power delivery assessments, generates design guidelines, and communicates technical recommendations to internal design teams and external customers.

Base salary range: $179,000–$269,000 (U.S.).

Experience Level

Senior — requires extensive experience; posting specifies over 15 years of experience in DDR/HBM SIPI engineering.

Responsibilities

Primary responsibilities include technical analysis, documentation, and cross-team/customer communication.

• Perform interconnect assessments using advanced modeling to predict channel data rates and signal margins.
• Evaluate system performance optimization strategies, including FFE, DFE, and CTLE equalization techniques.
• Assess power delivery systems to optimize supply stability and minimize jitter.
• Construct and analyze eye diagrams using statistical modeling and evaluate return loss, impedance matching, and resonant behavior.
• Document findings in reports and design guidelines for PHY and board designs.
• Present results and recommendations to internal design teams and external customers to improve PHY/system performance.
• Collaborate with multi-site teams and track memory vendor roadmaps and standards committee activity to inform design strategy.

Requirements

Must-have technical skills and experience; nice-to-have items noted where applicable.

• Extensive experience with DDR/HBM SIPI and high-speed interface signaling (s-parameters, channel loss, crosstalk, jitter, equalization).
• Strong knowledge of signal and power integrity analysis methods (eye diagram construction via statistical modeling, return loss, impedance matching, resonant systems).
• Proficiency with HFSS and Ansys toolsets and circuit/signal simulators such as HSPICE, Raptor, and ADS.
• Ability to generate clear technical reports, recommendations, and design guidelines for engineers and customers.
• Familiarity with board-level construction and on-chip I/O behavior; experience working across multi-site design teams.
• Effective verbal and written communication skills and ability to drive issues to closure independently.
• Nice-to-have: direct PHY design experience and active involvement with standards or memory vendor roadmaps.

Education Requirements

Not specified.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.